NEC V850/SA1 mPD703015 Preliminary User's Manual page 320

Figure 12-4. Format of DMA Channel Control Registers 0 to 2 (DCHC0 to DCHC2) (2/2)
TDIRn
0
1
DSn
0
1
ENn
0
1
Note Make sure that the transfer format conforms to the peripheral I/O register specifications (access-
enabled data size, read/write, etc.) for the DMA peripheral I/O address registers (DIOA0 to DIOA2).
320
CHAPTER 12
Transfer Direction Control Between Peripheral I/Os and On-Chip RAM
From on-chip RAM to peripheral I/Os
From peripheral I/Os to on-chip RAM
Control of Transfer Data Size for DMA Transfer
8-bit transfer
16-bit transfer
Control of DMA Transfer Enable/Disable Status
Disable
Enable (reset to "0" after DMA transfer is completed)
DMA FUNCTIONS
Note
Note