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Figure 10-9. Format of IIC Control Register (IICC0) (3/4)
ACKE
0
Disable acknowledge.
1
Enable acknowledge. During the ninth clock period, the SDA line is set to low level. However, the ACK is
invalid during address transfers and is valid when EXC = 1.
Condition for clearing (ACKE = 0)
• Cleared by instruction
• When RESET is input
STT
Does not generate a start condition.
0
1
When bus is released (during STOP mode):
Generates a start condition (for starting as master). The SDA line is changed from high level to low level
and then the start condition is generated. Next, after the rated amount of time has elapsed, SCL is
changed to low level.
When bus is not used:
This trigger functions as a start condition reserve flag. When set, it releases the bus and then
automatically generates a start condition.
Wait state (in master mode):
Releases the wait and generates the start condition.
Cautions concerning set timing
• For master reception
• For master transmission : Note that a start condition cannot be generated normally during the ACK period.
• Cannot be set at the same time as SPT
Condition for clearing (STT = 0)
• Cleared by instruction
• Cleared by loss in arbitration
• Cleared after start condition is generated by master
device
• Cleared when RESET is input
Note This flag's signal is invalid when IICE = 0.
Remark
Bit 1 (STT) is 0 when it is read after data setting.
CHAPTER 10 SERIAL INTERFACE FUNCTION
Acknowledge Control
Note
Start Condition Trigger
: Cannot be set during transfer. Can be set only when ACKE has been set to 0 and slave
has been notified of final reception.
Note
Condition for setting (ACKE = 1)
• Set by instruction
Condition for setting (STT = 1)
• Set by instruction
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