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Fig. No.
9-2
Format of Oscillation Stabilization Time Selection Register (OSTS) ......................................................
9-3
Format of Watchdog Timer Clock Selection Register (WDCS)...............................................................
9-4
Format of Watchdog Timer Mode Register (WDTM) ..............................................................................
9-5
Format of Oscillation Stabilization Time Selection Register (OSTS) ......................................................
10-1
Block Diagram of 3-wire Serial I/O..........................................................................................................
10-2
Format of Serial Operation Mode Register 0-2 (CSIM0-CSIM2) ............................................................
10-3
Format of Serial Clock Selection Registers 0-2 (CSIS0-CSIS2).............................................................
10-4
Format of Serial Operation Mode Register 0-2 (CSIM0-CSIM2) ............................................................
10-5
Format of Serial Operation Mode Registers 0-2 (CSIM0-CSIM2)...........................................................
10-6
Timing of 3-wire Serial I/O Mode ............................................................................................................
10-7
Block Diagram of I
10-8
Serial Bus Configuration Example Using I
10-9
Format of IIC Control Register (IICC0) ...................................................................................................
10-10
Format of IIC Status Register (IICS0).....................................................................................................
10-11
Format of IIC Clock Select Register (IICCL0).........................................................................................
10-12
Pin Configuration Diagram......................................................................................................................
2
10-13
I
C Bus's Serial Data Transfer Timing ....................................................................................................
10-14
Start Conditions ......................................................................................................................................
10-15
Address ..................................................................................................................................................
10-16
Transfer Direction Specification..............................................................................................................
10-17
ACK Signal .............................................................................................................................................
10-18
Stop Condition ........................................................................................................................................
10-19
Wait Signal .............................................................................................................................................
10-20
Arbitration Timing Example.....................................................................................................................
10-21
Communication Reservation Timing.......................................................................................................
10-22
Timing for Accepting Communication Reservations ...............................................................................
10-23
Communication Reservation Flow Chart ................................................................................................
10-24
Master Operation Flow Chart..................................................................................................................
10-25
Slave Operation Flow Chart....................................................................................................................
10-26
Example of Master to Slave Communication
(when 9-clock Wait Is Selected for Both Master and Slave)...................................................................
10-27
Example of Slave to Master Communication
(when 9-clock Wait Is Selected for Both Master and Slave)...................................................................
10-28
Block Diagram of UARTn........................................................................................................................
10-29
Format of Asynchronous Serial Interface Mode Register 0, 1 (ASIM0, ASIM1) .....................................
10-30
Format of Asynchronous Serial Interface Status Registers 0, 1 (ASIS0, ASIS1) ...................................
10-31
Format of Baud Rate Generator Control Registers 0, 1 (BRGC0, BRGC1)............................................
10-32
Format of Baud Rate Generator Mode Control Registers 0, 1 (BRGMC0, BRGMC1)............................
10-33
Error Tolerance (when k = 0), including Sampling Errors .......................................................................
10-34
Format of Transmit/Receive Data in Asynchronous Serial Interface ......................................................
10-35
Timing of Asynchronous Serial Interface Transmit Completion Interrupt ...............................................
10-36
Timing of Asynchronous Serial Interface Receive Completion Interrupt ................................................
10-37
Receive Error Timing ..............................................................................................................................
LIST OF FIGURES (3/5)
2
C...............................................................................................................................
2
C Bus ...................................................................................
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