Watchdog Timer Mode Register (Wdtm); Noise Elimination - NEC Renesas V850/SC1 User Manual

7.3.7 Watchdog timer mode register (WDTM)

This register can be read/written in 8- or 1-bit units (for details, refer to CHAPTER 10 WATCHDOG TIMER).
After reset: 00H R/W
Symbol <7>
WDTM RUN
RUN
0 Count operation stopped
1 Count started after clearing
WDTM4
0 Interval timer mode
1 WDT mode
WDTM3
0 When overflow occurs, the internal reset signal is not generated
1 When overflow occurs, the internal reset signal is generated
Caution If the RUN, WDTM4, or WDTM3 bit is set to 1, that bit can only be cleared by reset input.

7.3.8 Noise elimination

(1) Elimination of noise from INTP0 to INTP3 and INTP7 to INTP9 pins
An on-chip noise eliminator is provided that uses analog delay to eliminate noise. Consequently, if a signal
having a constant level is input for longer than a specified time, it is detected as a valid edge.
Edge detection occurs only after the specified amount of time has elapsed.
(2) Elimination of noise from INTP4 and INTP5 pins
A digital noise eliminator is provided on chip. If the input level of the INTP pin is detected by the sampling clock
(f ) and the same level is not detected three successive times, the input pulse is eliminated as noise. Note the
XX
following:
•
If the input pulse width is 2 or 3 clocks, whether it will be detected as a valid edge or eliminated as noise is
undetermined.
To securely detect a valid edge, the same level input of 3 clocks or more is required.
•
When a noise is generated in synchronization with a sampling clock, this may not be recognized as a noise.
In this case, eliminate the noise by adding a filter to the input pin.
238
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Address: FFFFF384H
6 5 4
0 0 WDTM4
Watchdog timer operation control
Timer mode selection/interrupt control by WDT
Internal reset signal generation selection
User's Manual U15109EJ3V0UD
3 2 1
WDTM3 0 0
0
0