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(iii) R/W (Read/Write Status) ··· output
In this mode, this pin is output for the status signal that indicates whether the bus cycle is a read cycle
or write cycle during external access. High level is set during the read cycle and low level is set during
the write cycle. The output changes in synchronization with the rising edge of the clock in the T1 state
of the bus cycle. High level is set when the timing sets the bus cycle as inactive.
(iv) DSTB (Data Strobe) ··· output
In this mode, this pin is output pin for the external data bus's access strobe signal. Output becomes
active (low level) during the T2 and TW states of the bus cycle. Output becomes inactive (high level)
when the timing sets the bus cycle as inactive.
(v) ASTB (Address Strobe) ··· output
In this mode, this pin is output pin for the external address bus's latch strobe signal. Output becomes
active (low level) in synchronization with the falling edge of the clock during the T1 state of the bus
cycle, and becomes inactive (high level) in synchronization with the falling edge of the clock during the
T3 state of the bus cycle. Output becomes inactive when the timing sets the bus cycle as inactive.
(vi) HLDAK (Hold Acknowledge) ··· output
In this mode, this pin is output pin for the acknowledge signal that indicates high impedance status for
the address bus, data bus, and control bus when the V850/SA1 receives a bus hold request.
The address bus, data bus, and control bus are set to high impedance status when this signal is active.
(vii) HLDRQ (Hold Request) ··· input
In this mode, this pin is input pin by which an external device requests the V850/SA1 to release the
address bus, data bus, and control bus. This pin accepts asynchronous input for CLKOUT. When this
pin is active, the address bus, data bus, and control bus are set to high impedance status. This occurs
either when the V850/SA1 completes execution of the current bus cycle or immediately if no bus cycle
is being executed, then the HLDAK signal is set as active and the bus is released.
(viii) WRL (Write Strobe Low Level Data) ··· output
In this mode, this is write strobe signal output pin for the low-order data in an external 16-bit data bus.
Output occurs during the write cycle, similar to DSTB.
CHAPTER 2
PIN FUNCTIONS
45
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