NEC V850/SA1 mPD703015 Preliminary User's Manual page 192

32-/16-bit single-chip microcontrollers
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(2) Cascade connection (16-bit timer) mode
The V850/SA1 provides a 16-bit register that can be used when connecting in cascade.
Available registers are as follows.
TM2-TM3 cascade connection: 16-bit counter TM23 (Address: FFFFF24AH)
TM4-TM5 cascade connection: 16-bit counter TM45 (Address: FFFFF26AH)
• Operating as an interval timer (16-bit resolution)
By setting bit 4 (TMCn4) of the 8-bit timer mode control register n (TMCn) to "1," the timer enters the
timer/counter mode with 16-bit resolution.
With the count preset in the 8-bit compare register n (CRn0) as the interval, the timer operates as an interval
timer by repeatedly generating interrupts.
Setting method
(1) Set each register.
• TCLn
: The lowest-order timer selects the count clock.
cascade are not used in setting.
• CRn0
: Compare values (Each compare value can be set from 00H to FFH.)
• TMCn
: Select the clear and start mode when TMn and CRn0 match.
Lowest-order timer → TMCn = 0000xxx0B, x: don't care
Other timer → TMCn = 0001xxx0B, x: don't care
(2) Setting TCEn = 1 for the high-order timer and finally setting TCEn = 1 in the low-order timer starts the
count operation.
(3) If the values of TMn of all timers connected in cascade and CRn0 match, the lowest-order INTTMn is
generated (All TMns are cleared to 00H) .
(4) INTTMn are repeatedly generated at the same interval.
Cautions 1. Always set the compare register n (CRn0) after stopping timer operation.
2. If the high-order count matches CRn0 even when used in a cascade connection, the high-
order INTTMn is generated. Always mask the high-order timer in order to disable interrupts.
3. The TCEn setting begins at the high-order timer. Set the lowest-order timer last.
4. Restarting and stopping the count is possible by setting only 1 or 0 in TCEn of the lowest-
order timer to start and stop it.
192
CHAPTER 7
TIMER/COUNTER FUNCTION
16-bit compare register CR23 (Address: FFFFF24CH)
16-bit compare register CR45 (Address: FFFFF26CH)
The high-order timers connected in

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