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Fig. No.
7-11
Control Register Settings for Pulse Width Measurement with
Free Running Counter and One Capture Register ................................................................................
7-12
Configuration for Pulse Width Measurement with Free Running Counter .............................................
7-13
Timing of Pulse Width Measurement with Free Running Counter and
One Capture Register (with both edges specified) ................................................................................
7-14
Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter .............
7-15
CRn1 Capture Operation with Rising Edge Specified............................................................................
7-16
Timing of Pulse Width Measurement with Free Running Counter (with both edges specified) .............
7-17
Control Register Settings for Pulse Width Measurement
with Free Running Counter and Two Capture Registers .......................................................................
7-18
Timing of Pulse Width Measurement with Free Running Counter and
Two Capture Registers (with rising edge specified)...............................................................................
7-19
Control Register Settings for Pulse Width Measurement by Restarting ................................................
7-20
Timing of Pulse Width Measurement by Restarting (with rising edge specified) ...................................
7-21
Control Register Settings in External Event Counter Mode ...................................................................
7-22
Configuration of External Event Counter ...............................................................................................
7-23
Timing of External Event Counter Operation (with rising edge specified)..............................................
7-24
Control Register Settings in Square Wave Output Mode.......................................................................
7-25
Timing of Square Wave Output Operation.............................................................................................
7-26
Control Register Settings for One-Shot Pulse Output with Software Trigger.........................................
7-27
Timing of One-Shot Pulse Output Operation with Software Trigger ......................................................
7-28
Control Register Settings for One-Shot Pulse Output with External Trigger..........................................
7-29
Timing of One-Shot Pulse Output Operation with External Trigger (with rising edge specified)............
7-30
Start Timing of 16-Bit Timer Register n..................................................................................................
7-31
Timing after Changing Compare Register during Timer Count Operation .............................................
7-32
Data Hold Timing of Capture Register ...................................................................................................
7-33
Operation Timing of OVFn Flag .............................................................................................................
7-34
Block Diagram of TM2-TM5 ...................................................................................................................
7-35
Format of TM2, TM3 Timer Clock Selection Register 2 and 3 (TCL2, TCL3) ........................................
7-36
Format of TM4, TM5 Timer Clock Selection Register 4 and 5 (TCL4, TCL5) ........................................
7-37
Format of 8-Bit Timer Mode Control Register 2-5 (TMC2-TMC5) ..........................................................
7-38
Timing of Interval Timer Operation ........................................................................................................
7-39
Timing of External Event Counter Operation (when rising edge is set) .................................................
7-40
Timing of PWM Output...........................................................................................................................
7-41
Timing of Operation Based on CRn0 Transitions ..................................................................................
7-42
Cascade Connection Mode with 16-Bit Resolution................................................................................
7-43
Start Timing of Timer n ..........................................................................................................................
7-44
Timing After Compare Register Changes During Timer Counting .........................................................
8-1
Block Diagram of Watch Timer ..............................................................................................................
8-2
Format of Watch Timer Mode Control Register (WTM) .........................................................................
8-3
Operation Timing of Watch Timer/Interval Timer ...................................................................................
9-1
Block Diagram of Watchdog Timer ........................................................................................................
16
LIST OF FIGURES (2/5)
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