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Figure 6-1. Format of Processor Clock Control Register (PCC) (2/2)
Note
CK2
CK1
0
0
0
0
0
1
0
1
1
X
Note If manipulating CK2, do so in 1-bit units. In the case of 8-bit manipulation, do not change the values of
FLMD, CK1, and CK0.
Cautions 1. Even if the MCK bit is set to 1 during main clock operation, the main clock is not stopped.
The CPU clock stops after the sub clock is selected.
2. The following cautions apply to changing the FLMD bit.
• The FLMD bit is valid only for the µ µ µ µ PD70F3017 and 70F3017Y (flash memory
incorporated). In the µ µ µ µ PD703015 and 703015Y (mask ROM incorporated), the FLMD bit
can be read/written, but the low-power-consumption mode/low-speed mode cannot be
selected.
• The setting FLMD = 1 is valid only when the CPU clock is less than 5 MHz.
If the CPU clock is 5 MHz or higher, runaway may occur.
• If the CPU clock is changed to the sub clock, be sure to do so after setting the FLMD bit
to 0. When changing the CPU clock to the sub clock when the FLMD bit is 1, first set
the FLMD bit to 0, and then set CK2 bit to 1.
If the CK2 bit is set to 1 (sub clock operation) when the FLMD bit is 1, runaway may
occur.
Remark X:don't care
CHAPTER 6
CLOCK GENERATION FUNCTION
CK0
0
f
xx
1
f
/2
xx
0
f
/4
xx
1
f
/8
xx
X
f
(sub clock)
xt
Selection of CPU Clock
133
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