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(2) IDLE mode
This mode stops the entire system by stopping the CPU's operating clock as well as the operating clock for on-
chip peripheral functions while the clock oscillator is still operating. However, the sub clock continues to operate
and supplies a clock to the on-chip peripheral functions.
When this mode is canceled, there is no need for the oscillator to wait for the oscillation stabilization time, so
normal operation can be resumed quickly.
When the power saving control register (PSC)'s IDLE bit is set (to "1"), the system switches to IDLE mode.
(3) Software STOP mode
This mode stops the entire system by stopping a clock oscillator that is not for a sub clock system. The sub
clock continues to be supplied to keep on-chip peripheral functions operating. If a sub clock is not used, ultra low
power consumption mode (leak current only) is set. STOP mode setting is prohibited if the CPU is operating via
the sub clock.
When using an external clock, set (to "1") the CKSEL bit in the PSC register.
If the PSC register's STP bit is set (to "1"), the system enters STOP mode.
(4) Sub clock operation
Under this mode, the CPU clock is set to operate using the sub clock and the PCC register's MCK bit is set (to
"1") to set low power consumption mode during which the entire system operates using only the sub clock.
When HALT mode has been set, the CPU's operating clock is stopped so that power consumption can be
reduced.
When IDLE mode has been set, the CPU's operating clock and some peripheral functions (DMAC and BCU) are
stopped, so that power consumption can be reduced even lower than when in HALT mode.
6.4.2 HALT mode
(1) Settings and operating states
When in this mode, the clock's oscillator continues to operate but the CPU's operating clock is stopped. A clock
continues to be supplied for other on-chip peripheral functions to maintain operation of those functions. When
HALT mode is set while the CPU is idle, it enables the system's total power consumption to be reduced.
When in HALT mode, execution of programs is stopped but the contents of all registers and on-chip RAM are
retained as they were just before HALT mode was set. In addition, all on-chip peripheral functions that do not
depend on instruction processing by the CPU continue operating.
HALT mode can be set by executing the HALT instruction. It can be set when the CPU is operating via either the
main clock or sub clock.
The operating statuses during normal HALT mode are listed in Table 6-1.
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CHAPTER 6
CLOCK GENERATION FUNCTION
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