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(7) Bus hold timing
CLKOUT (input)
HLDRQ (input)
HLDAK (output)
A16 to A21 (output)
A1 to A15 (output)
AD0 to AD15
Address
(input/output)
ASTB (output)
R/W (output)
DSTB, RD,
WRH, WRL (output)
UBEN, LBEN (output)
WAIT (input)
Notes 1. If HLDRQ signal is inactive (high-level) at the sampling timing, bus hold state is not entered.
2. If transmitted to bus hold status after write cycle, high-level may be output momentarily from R/W
pin immediately before HLDAK signal transmits from high-level to low-level.
Remarks 1. { indicates the sampling timing when the number of programmable waits is set to 0.
2. The broken line indicates the high-impedance state.
98
CHAPTER 4
BUS CONTROL FUNCTION
T2
T3
TH
Note1
Address
Data
TH
TH
TH
Address
Note2
TI
T1
Address
Undefined
Address
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