Table of Contents
Advertisement
10.3.6 Interrupt request (INTIIC0) generation timing and wait control
The setting of bit 3 (WTIM) in the IIC control register (IICC0) determines the timing by which INTIIC0 is generated
and the corresponding wait control, as shown in Table 10-3.
WTIM
Address
Notes 1, 2
9
0
Notes 1, 2
9
1
Notes 1.
The slave device's INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when
there is a match with the address set to the slave address register (SVA0).
At this point, ACK is output regardless of the value set to IICC0's bit 2 (ACKE). For a slave device that
has received an extension code, INTIIC0 occurs at the falling edge of the eighth clock.
2.
If the received address does not match the contents of the slave address register (SVA0), neither INTIIC0
nor a wait occurs.
Remark
The numbers in the table indicate the number of the serial clock's clock signals. Interrupt requests and
wait control are both synchronized with the falling edge of these clock signals.
260
CHAPTER 10 SERIAL INTERFACE FUNCTION
Table 10-3. INTIIC0 Timing and Wait Control
During slave device operation
Data reception
Data transmission
Note 2
8
Note 2
9
During master device operation
Address
Note 2
8
9
Note 2
9
9
Data reception
Data transmission
8
8
9
9
Advertisement
Table of Contents
