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9.2 Configuration
The watchdog timer consists of the following hardware.
Item
Control registers
9.3 Watchdog Timer Control Register
Three registers control the watchdog timer.
• Oscillation stabilization time selection register (OSTS)
• Watchdog timer clock selection register (WDCS)
• Watchdog timer mode register (WDTM)
(1) Oscillation stabilization time selection register (OSTS)
This register selects the oscillation stabilization time after a reset is applied or the STOP mode is released until
the oscillation is stable.
OSTS is set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H.
Figure 9-2. Format of Oscillation Stabilization Time Selection Register (OSTS)
After reset: 04H
7
OSTS
0
OSTS2
0
0
0
0
1
Otherwise
Note Parenthesized values apply when fxx = 17 MHz.
CHAPTER 9
WATCHDOG TIMER
Table 9-3. Watchdog Timer Configuration
Oscillation stabilization time selection register (OSTS)
Watchdog timer clock selection register (WDCS)
Watchdog timer mode register (WDTM)
R/W
Address: FFFFF380H
6
5
4
0
0
0
OSTS1
OSTS0
/fxx (964 µ s)
14
0
0
2
16
0
1
2
/fxx (3.855 ms)
17
1
0
2
/fxx (7.710 ms)
18
1
1
2
/fxx (15.42 ms)
19
0
0
2
/fxx (30.84 ms)
Setting prohibited
Configuration
3
2
0
OSTS2
OSTS1
Oscillation Stabilization Time Selection
1
0
OSTS0
Note
203
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