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(2) Measurement of two pulse widths with free running counter
The pulse widths of the two signals respectively input to the TIn0 and TIn1 pins can be measured when the 16-
bit timer register n (TMn) is used as a free running counter (refer to Figure 7-14).
When the edge specified by bits 4 and 5 (ESn00 and ESn01) of the prescaler mode register n (PRMn) is input to
the TIn0 pin, the value of the TMn is loaded to the 16-bit capture/compare register n1 (CRn1) and an external
interrupt request signal (INTTMn1) is set.
When the edge specified by bits 6 and 7 (ESn10 and ESn11) is input to the TIn1 pin, the value of TMn is loaded
to the 16-bit capture/compare register n0 (CRn0), and an external interrupt request signal (INTTMn0) is set.
The edges of the TIn0 and TIn1 pins are specified by bits 4 and 5 (ESn00 and ESn01) and bits 6 and 7 (ESn10
and ESn11) of PRMn, respectively. The rising, falling, or both rising and falling edges can be specified.
The valid edge is detected through sampling at a count clock cycle selected by the prescaler mode register n
(PRMn), and the capture operation is not performed until the valid level is detected two times. Therefore, noise
with a short pulse width can be rejected.
Figure 7-14. Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter
TMCn
0
0
CRCn
0
0
Remark 0/1: When these bits are reset to 0 or set to 1, the other functions can be used along with the pulse
width measurement function. For details, refer to Figures 7-2 and 7-3.
CHAPTER 7
TIMER/COUNTER FUNCTION
(a) 16-bit timer mode control register 0, 1 (TMC0, TMC1)
TMCn3
0
0
(b) Capture/compare control register 0, 1 (CRC0, CRC1)
0
0
TMCn2
TMCn1
0
1
0/1
CRCn2
CRCn1
0
1
0
OVFn
0
Free running mode
CRCn0
1
CRn0 as capture
register
Captures valid edge of
TIn1 pin to CRn0.
CRn1 as capture
register
163
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