Timing Of Asynchronous Serial Interface Receive Completion Interrupt - NEC V850/SA1 mPD703015 Preliminary User's Manual

(iv) Reception
The receive operation is enabled when "1" is set to bit 6 (RXEn) of the asynchronous serial interface mode
register (ASIMn), and input via the RxDn pin is sampled.
The serial clock specified by ASIMn is used when sampling the RxDn pin.
When the RxDn pin goes low, the 5-bit counter begins counting and the start timing signal for data sampling
is output when half of the specified baud rate time has elapsed. If sampling the RxDn pin input with this start
timing signal yields a low-level result, a start bit is recognized, after which the 5-bit counter is initialized and
starts counting and data sampling begins. After the start bit is recognized, the character data, parity bit, and
one-bit stop bit are detected, at which point reception of one data frame is completed.
Once reception of one data frame is completed, the receive data in the shift register is transferred to the
receive buffer register (RXBn) and a receive completion interrupt (INTSRn) occurs.
Even if an error has occurred, the receive data in which the error occurred is still transferred to RXBn.
When an error occurs, INSTRn is generated if bit 1 (ISRMn) of ASIMn is cleared (0). On the other hand,
INSTRn is not generated if the ISRMn bit is set (1).
If the RXEn bit is reset (to "0") during a receive operation, the receive operation is stopped immediately. At
this time, the contents of RXBn and ASISn do not change, nor does INTSRn or INTSERn occur.
Figure 10-36 shows the timing of the asynchronous serial interface receive completion interrupt.
Figure 10-36. Timing of Asynchronous Serial Interface Receive Completion Interrupt
RxDn (input)
INTSRn
Caution Be sure to read the contents of the receive buffer register (RXBn) even when a receive
error has occurred. If the contents of RXBn are not read, an overrun error will occur
during the next data receive operation and the receive error status will remain.
Remark
n = 0, 1
298
CHAPTER 10 SERIAL INTERFACE FUNCTION
START D0 D1 D2 D6 D7 Parity STOP