NEC V850/SA1 mPD703015 Preliminary User's Manual page 379

Instruction Set (alphabetical order) (2/4)
Mnemonic Operand
LD.W disp16 rrrrr111001RRRRR
[reg1], reg2 ddddddddddddddd1
LDSR reg2, regID rrrrr111001RRRRR
ddddddddddddddd1 ← GR [reg2]
MOV reg1, reg2 rrrrr000000RRRRR
imm5, reg2 rrrrr010000iiiii
MOVEA imm16, rrrrr110001RRRRR
reg1, reg2 iiiiiiiiiiiiiiii
MOVHI imm16, rrrrr110010RRRRR
reg1, reg2 iiiiiiiiiiiiiiii
MULH reg1,reg2 rrrrr000111RRRRR
imm5, reg2 rrrrr010111iiiii
MULHI imm16, rrrrr110111RRRRR
reg1, reg2 iiiiiiiiiiiiiiii
NOP 0000000000000000 Uses 1 clock cycle without doing anything
NOT reg1, reg2 rrrrr000001RRRRR
NOT1 bit#3, 01bbb111110RRRRR
disp16 [reg1] dddddddddddddddd
OR reg1, reg2 rrrrr001000RRRRR
ORI imm16, rrrrr110100RRRRR
reg1, reg2 iiiiiiiiiiiiiiii
RETI 0000011111100000
0000000101000000
Notes 1. ddddddddddddddd is the higher 15 bits of disp 16.
2. The op code of this instruction uses the field of reg1 through the source register is shown as reg2 in
the above table. Therefore, the meaning of register specification for mnemonic description and op code
is different from that of the other instructions.
rrr = regID specification
RRRRR = reg2 specification
3. Only the lower half-word data is valid.
APPENDIX B LIST OF INSTRUCTION SET
Op Code
adr ← GR [reg1] + sign-extend (disp16)
GR [reg2] ← Load-memory (adr, Wortd))
Note 1
SR [regID]
Note 2
GR [reg2] ← GR [reg1]
GR [reg2] ← sign-extend (imm5)
GR [reg2] ← GR [reg1] + sign-extend
(imm16)
GR [reg2] ← GR [reg1] + (imm16 || 0
GR [reg2] ← GR [reg2]
(Signed multiplication)
GR [reg2] ← GR [reg2]
(imm5) (Signed multiplication)
GR [reg2] ← GR [reg1]
(Signed multiplication)
GR [reg2] ← NOT (GR [reg1])
adr ← GR [reg1] + sign-extend (disp16)
Z flag ← Not (Load-memory-bit
(adr, bit#3))
Store-memory-bit (adr, bit#3, Z flag)
GR [reg2] ← GR [reg2] OR GR [reg1]
GR [reg2] ← GR [reg2] OR zero-extend
(imm16)
if PSW.EP = 1
← EIPC
then PC
PSW ← EIPSW
eise if PSW.NP = 1
then PC
PSW ← FEPSW
eise PC
PSW ← EIPSW
Execution
Operation
i
1
regID = EIPC, FEPC 1
regID = EIPSW, FEPSW
regID = PSW
1
1
1
16
) 1
Note 3 × GR [reg1] Note 3
1
Note 3
× sign-extend
1
Note 3
× imm16
1
1
1
4
1
1
4
← FEPC
← EIPC
Flag
Clock
r l CY OV S Z
1 2
1 3
1
× × × ×
1
1 1
1 1
1 1
1 1
1 2
1 2
1 2
1 1
× ×
1 1 0
×
4 4
× ×
1 1 0
× ×
1 1 0
4 4 R R R R
SAT
×
R
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