Example Of Interrupt Nesting Process - NEC V850/SA1 mPD703015 Preliminary User's Manual

32-/16-bit single-chip microcontrollers
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Main routine
EI
Interrupt request a
(level 3)
Interrupt request c
(level 3)
Interrupt request e
(level 2)
Interrupt request g
(level 1)
Remarks 1. a to u in the figure are the names of interrupt requests shown for the sake of explanation.
2. The default priority in the figure indicates the relative priority between two interrupt requests.
Caution The values of EIPC and EIPSW must be saved before executing multiple interrupts.
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CHAPTER 5
INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 5-8. Example of Interrupt Nesting Process (1/2)
Processing of a
EI
Interrupt
request b
(level 2)
Processing of c
Interrupt request d
(level 2)
Processing of d
Processing of e
EI
Interrupt request f
(level 3)
Processing of f
Processing of g
EI
Interrupt request h
(level 1)
Processing of h
Processing of b
Interrupt request b is accepted because the priority of
b is higher than that of a and interrupts are enabled.
Although the priority of interrupt request d is higher
than that of c, d is kept pending because interrupts
are disabled.
Interrupt request f is kept pending even if interrupts are
enabled because its priority is lower than that of e.
Interrupt request h is kept pending even if interrupts are
enabled because its priority is the same as that of g.

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