Format Of Iic Clock Select Register (Iiccl0) - NEC V850/SA1 mPD703015 Preliminary User's Manual

(3) IIC clock select register (IICCL0)
This register is used to set the transfer clock for the I
IICCL0 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets IICCL0 to 00H.
Figure 10-11. Format of IIC Clock Select Register (IICCL0) (1/2)
Note
After reset : 00H R/W
Symbol
7 6
IICCL0 0 0
CLD
0 SCL line was detected at low level.
1 SCL line was detected at high level.
Condition for clearing (CLD = 0)
• When the SCL line is at low level
• When IICE = 0
• When RESET is input
DAD
0 SDA line was detected at low level.
1 SDA line was detected at high level.
Condition for clearing (DAD = 0)
• When the SDA line is at low level
• When IICE = 0
• When RESET is input
Note Bits 4 and 5 are read-only bits.
Remark IICE: Bit 7 of IIC control register (IICC0)
230
CHAPTER 10 SERIAL INTERFACE FUNCTION
2
C bus.
Address: FFFFF344H
5 4
3
CLD DAD SMC
Detection of SCL Line Level (valid only when IICE = 1)
Detection of SDA Line Level (valid only when IICE = 1)
2 1 0
DFC CL1 CL0
Condition for setting (CLD = 1)
• When the SCL line is at high level
Condition for setting (DAD = 1)
• When the SDA line is at high level