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Figure 10-2. Format of Serial Operation Mode Registers 0-2 (CSIM0-CSIM2) (2/2)
MODEn
0
1
SCLn2
0
0
0
0
1
1
Others
Caution Do not perform bit manipulation of the SCLn1 and SCLn0.
Remarks 1. Parenthesized values apply when fxx = 17 MHz.
2. Refer to Figure 10-3 for the SCLn2 bit.
Figure 10-3. Format of Serial Clock Selection Registers 0-2 (CSIS0-CSIS2)
After reset : 00H
7
CSISn
0
(n = 0-2)
Remark
Refer to Figure 10-2 for the setting of the SCLn2 bit.
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CHAPTER 10
SERIAL INTERFACE FUNCTION
Operation mode
Transmit/receive mode
Receive-only mode
SCLn1
SCLn0
0
0
External clock input (SCKn)
0
1
at n = 0: TO2
at n = 1, 2: TO3
1
0
fxx/8 (2.125 MHz)
1
1
fxx/16 (1.0626 MHz)
1
0
fxx/32 (531.3 kHz)
1
1
fxx/64 (265.6 kHz)
Setting prohibited
R/W
Address: CSIS0
6
5
0
0
Transfer Operation Mode Flag
Transfer start trigger
SIOn write
SIOn read
Clock Selection
FFFFF2A4H
CSIS1
FFFFF2B4H
CSIS2
FFFFF2C4H
4
3
0
0
SOn output
Normal output
Low level fixed
2
1
0
0
0
SCLn2
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