Error Detection; Extension Code - NEC V850/SA1 mPD703015 Preliminary User's Manual

10.3.8 Error detection

2
During I C bus mode, the status of the serial data bus (SDA) during data transmission is captured by the IIC shift
register (IIC0) of the transmitting device, so the IIC0 data prior to transmission can be compared with the transmitted
IIC0 data to enable detection of transmission errors. A transmission error is judged as having occurred when the
compared data values do not match.

10.3.9 Extension code

(1) When the high-order 4 bits of the receive address are either "0000" or "1111", the extension code flag (EXC) is
set for extension code reception and an interrupt request (INTIIC0) is issued at the falling edge of the eighth
clock. The local address stored in the slave address register (SVA0) is not affected.
(2) If "111110XX" is set to SVA0 by a 10-bit address transfer and "111110XX0" is transferred from the master
device, the results are as follows. Note that INTIIC0 occurs at the falling edge of the eighth clock.
• High-order four bits of data match: EXC = 1
• Seven bits of data match: COI = 1
Note EXC: Bit 5 of IIC status register (IICS0)
COI: Bit 4 of IIC status register (IICS0)
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension
code, such processing is performed by software.
For example, after the extension code is received, if you do not wish to operate the target device as a slave
device, you can set LREL = 1 to set standby mode for the next communication operation.
Slave address
0000 000
0000 000
0000 001
0000 010
1111 0XX
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CHAPTER 10 SERIAL INTERFACE FUNCTION
Note
Note
Table 10-4. Extension Code Bit Definitions
R/W bit
0 General call address
1 Start byte
X CBUS address
X Address that is reserved for different bus format
X 10-bit slave address specification
Description