NEC V850/SA1 mPD703015 Preliminary User's Manual page 370

Symbol
DBC0 DMA byte counter register 0
DBC1 DMA byte counter register 1
DBC2 DMA byte counter register 2
DCHC0 DMA channel control register 0
DCHC1 DMA channel control register 1
DCHC2 DMA channel control register 2
DIOA0 DMA peripheral I/O address register 0
DIOA1 DMA peripheral I/O address register 1
DIOA2 DMA peripheral I/O address register 2
DMAIC0 Interrupt control register
DMAIC1 Interrupt control register
DMAIC2 Interrupt control register
DRA0 DMA on-chip RAM address register 0
DRA1 DMA on-chip RAM address register 1
DRA2 DMA on-chip RAM address register 2
DWC Data wait control register
ECR Interrupt source register
EGN0 Falling edge specification register
EGP0 Rising edge specification register
EIPC Status saving register during interrupt
EIPSW Status saving register during interrupt
FEPC Status saving registers for NMI
FEPSW Status saving registers for NMI
IIC0 IIC shift register
IICC0 IIC control register
IICCL0 IIC clock selection register
IICS0 IIC status register
ISPR In-service priority register
MAM Memory address output mode register
MM Memory expansion mode register
OSTS Oscillation stabilisation time register
P0 Port 0
P1 Port 1
P2 Port 2
P3 Port 3
P4 Port 4
P5 Port 5
370
APPENDIX A REGISTER INDEX
Name
(2/5)
Unit Page
DMAC 318
DMAC 318
DMAC 318
DMAC 319
DMAC 319
DMAC 319
DMAC 317
DMAC 317
DMAC 317
INTC 117
INTC 117
INTC 117
DMAC 318
DMAC 318
DMAC 318
BCU 87
CPU 56
INTC 109, 332
INTC 109, 332
CPU 56
CPU 56
CPU 56
CPU 56
2
I C 231
2
I C 232
2
I C 230
2
I C 227
INTC 119
Port 71
Port 70
WDT 135, 203
Port 329
Port 336
Port 336
Port 339
Port 341
Port 341