NEC V850/SA1 mPD703015 Preliminary User's Manual page 378

Instruction Set (alphabetical order) (1/4)
Mnemonic Operand
ADD reg1, reg2 rrrrr001110RRRRR
imm5, reg2 rrrrr010010iiiii
ADDI imm16, rrrrr110000RRRRR
reg1, reg2
iiiiiiiiiiiiiiii
AND reg1, reg2 rrrrr110110RRRRR
ANDI imm16, rrrrr110110RRRRR
reg1, reg2 iiiiiiiiiiiiiiii
Bcond disp9 ddddd1011dddcccc
CLR1 bit#3, 10bbb111110RRRRR
disp16 dddddddddddddddd
[regf1]
CMP reg1, reg2 rrrrr001111RRRRR
imm5, reg2 rrrrr010011iiiii
DI 0000011111100000
0000000101100000
DIVH reg1, reg2 rrrrr000010RRRRR
EI 1000011111100000
0000000101100000
HALT 0000011111100000
0000000100100000
JARL disp22, reg2 rrrrr11110dddddd
ddddddddddddddd0
00000000011RRRRR PC ← GR [reg1]
JMP [reg1]
JR disp22 0000011110dddddd
ddddddddddddddd0
LD.B disp16 rrrrr111000RRRRR
[reg1], reg2 dddddddddddddddd
LD.H disp16 rrrrr111001RRRRR
[reg1], reg2 ddddddddddddddd0
Notes 1. dddddddd is the higher 8 bits of disp9.
2. Only the lower half-word is valid.
3. ddddddddddddddddddddd is the higher 21 bits of disp22.
4. ddddddddddddddd is the higher 15 bits of disp 16.
378
APPENDIX B LIST OF INSTRUCTION
Op Code
GR [reg2] ← GR [reg2] + GR [reg1]
GR [reg2] ← GR [reg2] + sign-extend
(imm5)
GR [reg2] ← GR [reg1] + sign-extend
(imm16)
GR [reg2] ← GR [reg2] AND GR [reg1]
GR [reg2] ← GR [reg1] AND zero-extend
(imm16)
if conditions are
Note 1
satisfied
then PC ← PC + sign-
extend (disp9)
adr ← GR [reg1] + sign-extend (disp16)
Z flag ← Not (Load-memory-bit
(adr, bit#3))
Store memory-bit (adr, bit#3, 0)
result ← GR [reg2] − GR [reg1]
result ← GR [reg2] − sign-extend (imm5)
PSW.ID ← 1
(Maskable interrupt disabled)
GR [reg2] ← GR [reg2] ÷ GR [reg2]
(signed division)
PSW.ID ← 0
(Maskable interrupt enabled)
Stops
GR [reg2] ← PC + 4
PC ← PC + sign-extend (disp22)
Note 3
PC ← PC + sign-extend (disp22)
Note 3
adr ← GR [reg1] + sign-extend (disp16)
GR [reg2] ← sign-extend (Load-memory
(adr, Byte))
adr ← GR [reg1] + sign-extend (disp16)
GR [reg2] ← sign-extend (Load-memory
Note 4
(adr, Halfword))
Execution
Operation
i
1
1
1
1
1
When condition 3
satisfied
1
When condition
not satisfied
4
1
1
1
Note 2
36
1
1
3
3
3
1
1
Flag
Clock
r l CY OV S Z
× × × ×
1 1
× × × ×
1 1
× × × ×
1 1
× ×
1 1 0
×
1 1 0 0
3 3
1 1
×
4 4
× × × ×
1 1
× × × ×
1 1
1 1
× × ×
36 36
1 1
1 1
3 3
3 3
3 3
1 2
1 2
SAT