Format Of Watchdog Timer Mode Register - NEC PD789860 User Manual

(2) Watchdog timer mode register (WDTM)
WDTM sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer.
This register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
Symbol <7> 6
WDTM RUN 0
RUN
0 Stops counting.
1 Clears counter and starts counting.
WDTM4 WDTM3
0 0
0 1
1 0
1 1
Notes 1. Once RUN has been set to 1, it cannot be cleared to 0 by software. Therefore, when counting is
started, it cannot be stopped by any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set to 1, they cannot be cleared to 0 by software.
3. The watchdog timer starts operation as an interval timer when RUN is set to 1.
Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up
to 0.8% shorter than the time set by the timer clock selection register 2 (TCL2).
2. To set watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming TMIF4 (bit 0 of
interrupt request flag register 0 (IF0)) being cleared to 0. When watchdog timer mode 1
or 2 is selected with TMIF4 set to 1, a non-maskable interrupt is generated upon the
completion of rewriting WDTM.
CHAPTER 10 WATCHDOG TIMER
Figure 10-3. Format of Watchdog Timer Mode Register
5 4 3
0 WDTM4 WDTM3
Watchdog timer operation selection
Watchdog timer operation mode selection
Operation stop
Interval timer mode (Generates a maskable interrupt upon overflow occurrence.)
Watchdog timer mode 1 (Generates a non-maskable interrupt upon overflow occurrence.)
Watchdog timer mode 2 (Starts a reset operation upon overflow occurrence.)
User's Manual U14826EJ5V0UD
2 1 0
0 0 0
Note 1
Address After reset R/W
FFF9H 00H R/W
Note 2
Note 3
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