NEC V850/SA1 mPD703015 Preliminary User's Manual page 239

(2) When master and slave devices both have a nine-clock wait
Master
IIC0
SCL
Slave
IIC0
SCL
ACKE H
Transfer lines
SCL
SDA
Output according to previously set ACKE value
Remarks ACKE : Bit 2 of IIC control register (IICC0)
WREL : Bit 5 of IIC control register (IICC0)
A wait may be automatically generated depending on the setting for bit 3 (WTIM) of the IIC control register (IICC0).
Normally, when bit 5 (WREL) of IICC0 is set to "1" or when FFH is written to the IIC shift register (IIC0), the wait
status is canceled and the transmitting side writes data to IIC0 to cancel the wait status.
The master device can also cancel the wait status via either of the following methods.
• By setting bit 1 (STT) of IICC0 to "1"
• By setting bit 0 (SPT) of IICC0 to "1"
CHAPTER 10 SERIAL INTERFACE FUNCTION
Figure 10-19. Wait Signal (2/2)
(master transmits, slave receives, and ACKE = 1)
Master and slave both wait
after output of ninth clock.
6 7 8 9
6 7 8 9
D2 D1 D0 ACK
IIC0 data write (cancel wait)
1 2 3
FFH is written to IIC0 or WREL is set to 1.
1 2 3
D7 D6 D5
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