Page 1 User’s Manual µ PD780344, 780354, 780344Y, 780354Y Subseries 8-Bit Single-Chip Microcontrollers µ PD780343 µ PD780343Y µ PD780344 µ PD780344Y µ PD780353 µ PD780353Y µ PD780354 µ PD780354Y µ PD78F0354 µ PD78F0354Y Document No. U15798EJ2V0UD00 (2nd edition) Date Published May 2003 N CP(K) 2002 Printed in Japan...
Page 2 [MEMO] User’s Manual U15798EJ2V0UD...
Page 3 C system, provided that the system conforms to the I C Standard Specification as defined by Philips. FIP, EEPROM, and IEBus are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 Major Revisions in This Edition (1/3) Page Description Throughout Deletion of indication “under development” for all target products pin → AV A/D converter operation enable voltage = 2.7 to 5.5 V → AV = 2.2 to 5.5 V p.33 Change of 113-pin plastic FBGA package in 1.4 Pin Configuration (Top View) p.52 Modification of Table 2-1 Pin I/O Circuit Types p.61...
Page 7 Major Revisions in This Edition (2/3) Page Description p.242 Change of Figure 12-16 Example of Connecting Capacitor to V and AV Pins in 1st edition to Figure 12-16 Example of Connecting Capacitor to AV p.243 Modification of Table 12-3 Resistances and Capacitances of Equivalent Circuit (Reference Values) p.245 Addition and modification of description in 13.2 (2) A/D conversion result register 0 (ADCR0), (3) Sample &...
Page 8 Major Revisions in This Edition (3/3) Page Description p.368 Modification of Figure 18-7 Format of Static/Dynamic Display Switching Register 3 (SDSEL3) p.369 Modification of Figure 18-8 Format of Pin Function Switching Registers (PF8 to PF11) and addition of Caution 2. pp.370, 371 Replace 18.4 LCD Controller/Driver Settings and 18.5 LCD Display RAM of 1st edition p.370 in 1st edition Deletion of Table 18-7 LCD Drive Voltages of 1st edition...
Page 9 INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the µ PD780344, 780354, 780344Y, and 780354Y Subseries and to design and develop application systems and programs for these devices. µ PD780344 Subseries: µ PD780343, 780344 µ...
Page 10 Conventions Data significance: Higher digits on the left and lower digits on the right ××× (overscore over pin or signal name) Active low representation: Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information ···...
Page 11 Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769E Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Page 12: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE ........................1.1 Features ........................... 1.2 Applications ..........................1.3 Ordering Information ......................1.4 Pin Configuration (Top View) ....................1.5 78K/0 Series Lineup ........................ 1.6 Block Diagram ......................... 1.7 Outline of Function ......................... 1.8 Mask Options .......................... CHAPTER 2 PIN FUNCTIONS ......................2.1 Pin Function List ........................
Page 13 3.2 Processor Registers ....................... 3.2.1 Control registers ........................... 3.2.2 General-purpose registers ......................3.2.3 Special-function registers (SFR) ....................3.3 Instruction Address Addressing ................... 3.3.1 Relative addressing ........................3.3.2 Immediate addressing ........................3.3.3 Table indirect addressing ......................3.3.4 Register addressing ........................3.4 Operand Address Addressing ....................3.4.1 Implied addressing ........................
Page 14 5.4.4 Divider ............................5.4.5 When no subsystem clocks are used ................... 5.5 Clock Generator Operations ....................122 5.5.1 Main system clock operations ...................... 5.5.2 Subsystem clock operations ......................5.6 Changing System Clock and CPU Clock Settings ............... 125 5.6.1 Time required for switchover between system clock and CPU clock ..........5.6.2 System clock and CPU clock switching procedure ...............
Page 15 9.3 Watch Timer Configuration ....................206 9.4 Registers to Control Watch Timer ..................206 9.5 Watch Timer Operations ......................209 9.5.1 Watch timer operation ........................9.5.2 Interval timer operation ......................... CHAPTER 10 WATCHDOG TIMER ....................210 10.1 Outline of Watchdog Timer ....................210 10.2 Watchdog Timer Functions ....................
Page 16 14.4 Operations of Serial Interface SIO3 ................... 269 14.4.1 Operation stop mode ........................14.4.2 3-wire serial I/O mode ........................ CHAPTER 15 SERIAL INTERFACE CSI1 ..................273 15.1 Functions of Serial Interface CSI1 ..................273 15.2 Configuration of Serial Interface CSI1 ................273 15.3 Registers to Control Serial Interface CSI1 ................
Page 17 18.3 Registers to Control LCD Controller/Driver ............... 363 18.4 LCD Display RAM ......................... 370 18.5 LCD Controller/Driver Settings .................... 371 18.6 Common Signals and Segment Signals ................372 18.7 Supplying LCD Drive Voltages V , and V ............. 375 LCD0 LCD1 LCD2 18.8 Display Modes ........................
Page 18 23.3.3 On-board pin processing ......................23.3.4 Connection of adapter for flash writing ..................CHAPTER 24 INSTRUCTION SET ....................444 24.1 Conventions .......................... 445 24.1.1 Operand identifiers and specification methods ................24.1.2 Description of “operation” column ....................24.1.3 Description of “flag operation” column ..................24.2 Operation List ........................
Page 19 LIST OF FIGURES (1/8) Figure No. Title Page Pin I/O Circuit List ..........................Memory Map ( µ PD780343, 780353, 780343Y, 780353Y) ..............Memory Map ( µ PD780344, 780354, 780344Y, 780354Y) ..............Memory Map ( µ PD78F0354, 78F0354Y) ..................... Correspondence Between Data Memory and Addressing ( µ...
Page 20 LIST OF FIGURES (2/8) Figure No. Title Page External Circuit of Subsystem Clock Oscillator ..................119 Examples of Incorrect Resonator Connection ..................120 Main System Clock Stop Function ....................... 123 System Clock and CPU Clock Switching ..................... 126 Block Diagram of 16-Bit Timer/Event Counter 0 .................. 128 Format of 16-Bit Timer Mode Control Register 0 (TMC0) ..............
Page 21 LIST OF FIGURES (3/8) Figure No. Title Page Block Diagram of Timer B0 ........................159 Block Diagram of Output Controller (Timer B0) ................... 160 Format of 8-Bit Timer Mode Control Register A0 ................. 163 Format of 8-Bit Timer Mode Control Register B0 ................. 164 Format of Carrier Generator Output Control Register B0 ..............
Page 22 LIST OF FIGURES (4/8) Figure No. Title Page Format of Watch Timer Interrupt Time Select Register (WTIM) ............208 Operation Timing of Watch Timer/Interval Timer .................. 209 10-1 Watchdog Timer Block Diagram ......................210 10-2 Format of Watchdog Timer Clock Select Register (WDCS) ..............213 10-3 Format of Watchdog Timer Mode Register (WDTM) ................
Page 23 LIST OF FIGURES (5/8) Figure No. Title Page 13-12 Full-Scale Error ............................ 257 13-13 Integral Linearity Error ......................... 257 13-14 Differential Linearity Error ........................257 13-15 Example of Series Resistor String Circuit Configuration ..............259 13-16 Analog Input Pin Connection ....................... 260 13-17 A/D Conversion End Interrupt Request Generation Timing ..............
Page 24 LIST OF FIGURES (6/8) Figure No. Title Page 17-9 Start Conditions ........................... 320 17-10 Address ..............................321 17-11 Transfer Direction Specification ......................321 17-12 ACK Signal ............................322 17-13 Stop Condition ............................. 323 17-14 Wait Signal ............................324 17-15 Arbitration Timing Example ........................346 17-16 Communication Reservation Timing ....................
Page 25 LIST OF FIGURES (7/8) Figure No. Title Page 19-5 Format of External Interrupt Rising Edge Enable Register (EGP), External Interrupt Falling Edge Enable Register (EGN) ............... 394 19-6 Format of Program Status Word ......................395 19-7 Flowchart of Non-Maskable Interrupt Request Generation to Acknowledgment ......... 19-8 Non-Maskable Interrupt Request Acknowledgment Timing ..............
Page 26 LIST OF FIGURES (8/8) Figure No. Title Page 23-12 Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O (CSI1) ..........442 23-13 Wiring Example for Flash Writing Adapter with UART (UART0) ............443 Configuration of Development Tools ....................487 TGC-100SDW Package Drawing (for Reference Only) ................
Page 27 LIST OF TABLES (1/3) Table No. Title Page Mask Options of Mask ROM Versions of µ PD780344, 780354 Subseries .......... Mask Options of Mask ROM Versions of µ PD780344Y, 780354Y Subseries ........Pin I/O Circuit Types ..........................Internal Memory Capacity ........................Vector Table ............................
Page 28 LIST OF TABLES (2/3) Table No. Title Page 12-1 8-Bit A/D Converter Configuration ....................... 224 12-2 Settings of ADCS0 and ADCE0 ......................228 12-3 Resistances and Capacitances of Equivalent Circuit (Reference Values) ........... 243 13-1 10-Bit A/D Converter Configuration ..................... 245 13-2 Settings of ADCS0 and ADCE0 ......................
Page 29 LIST OF TABLES (3/3) Table No. Title Page 21-1 Hardware Statuses After Reset ......................417 22-1 ROM Correction Configuration ......................419 Differences Between µ PD78F0354 and 78F0354Y, and Mask ROM Versions ........430 23-1 23-2 Memory Size Switching Register Settings ................... 431 23-3 Communication Mode List ........................
Page 30: Chapter 1 Outline
CHAPTER 1 OUTLINE 1.1 Features • Internal memory Type Program Memory Data Memory LCD Display RAM (ROM/Flash Memory) Part Number High-Speed RAM Expansion RAM µ PD780343, 780353, 40 × 8 bits 24 KB 512 bytes 512 bytes 780343Y, 780353Y µ PD780344, 780354, 32 KB 780344Y, 780354Y µ...
Page 31: Applications
CHAPTER 1 OUTLINE 1.2 Applications APS cameras, digital cameras, AV systems, household appliances, etc. 1.3 Ordering Information Part Number Package Internal ROM µ PD780343GC-×××-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Mask ROM µ PD780343F1-×××-DA3 113-pin plastic FBGA (10 × 10) Mask ROM µ...
Page 32: Pin Configuration (Top View)
CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) • 100-pin plastic LQFP (fine pitch) (14 × 14) P13/ANI3 P113/S39 P12/ANI2 P112/S38 P11/ANI1 P111/S37 P10/ANI0 P110/S36 P107/S35 P00/INTP0 P106/S34 P01/INTP1 P105/S33 P02/INTP2 P104/S32 P03/INTP3/ADTRG P103/S31 P04/INTP4 P102/S30 P05/INTP5/PCL P101/S29 P06/INTP6/TOB0 P100/S28 P07/TOA0/TMIB0 P97/S27 IC(V...
Page 33 CHAPTER 1 OUTLINE • 113-pin plastic FBGA (10 × 10) Top View Bottom View A B C D E F G H J K L Index mark Name Name Name Name Name Name P02/INTP2 P14/ANI4 P11/ANI1 P01/INTP1 CAPL P16/ANI6 P04/INTP4 RESET P21/SO3 P17/ANI7...
Page 34 CHAPTER 1 OUTLINE ADTRG: AD trigger input RESET: Reset ANI0 to ANI7: Analog input Receive data Analog power supply S0 to S39: Segment output Analog ground SCK1, SCK3, CAPH, CAPL: Capacitor for LCD SCL0: Serial clock COM0 to COM3: Common output for dynamic display SCOM0: Common output for static display Internally connected...
Page 35: Series Lineup
CHAPTER 1 OUTLINE 1.5 78K/0 Series Lineup The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries name. Products in mass production Products under development Y subseries products are compatible with I C bus. Control µ...
Page 36 CHAPTER 1 OUTLINE The major functional differences among the subseries are listed below. • Non-Y subseries Function Timer 8-Bit 10-Bit 8-Bit Serial Interface External Capacity MIN. Subseries Name (Bytes) 8-Bit 16-Bit Watch WDT A/D Expansion Value µ PD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch √...
Page 37 CHAPTER 1 OUTLINE • Y subseries Function Timer 8-Bit 10-Bit 8-Bit Serial Interface External Capacity MIN. Subseries Name 8-Bit 16-Bit Watch WDT A/D Expansion (Bytes) Value µ PD78078Y 48 K to 60 K 4 ch 1 ch 1 ch 1 ch 8 ch √...
Page 38: Block Diagram
CHAPTER 1 OUTLINE 1.6 Block Diagram TI00/P35 P00 to P07 Port 0 16-bit timer/ event counter 0 TO00/TI01/P34 P10 to P17 Port 1 TOA0/P07 8-bit timer A0 P20 to P27 Port 2 TOB0/P06 8-bit timer/ P30 to P35 Port 3 event counter B0 TMIB0/P07 P40 to P43...
Page 39: Outline Of Function
CHAPTER 1 OUTLINE 1.7 Outline of Function (1/2) µ PD780343 µ PD780344 µ PD780353 µ PD780354 µ PD78F0354 Part Number µ PD780343Y µ PD780344Y µ PD780353Y µ PD780354Y µ PD78F0354Y Item Note 1 Internal 24 KB 32 KB 24 KB 32 KB 32 KB memory...
Page 40 CHAPTER 1 OUTLINE (2/2) µ PD780343 µ PD780344 µ PD780353 µ PD780354 µ PD78F0354 Part Number µ PD780343Y µ PD780344Y µ PD780353Y µ PD780354Y µ PD78F0354Y Item Timer • 16-bit timer/event counter: 1 channel • 8-bit timer/event counter: 3 channels •...
Page 41: Mask Options
CHAPTER 1 OUTLINE 1.8 Mask Options The mask ROM versions ( µ PD780343, 780344, 780353, 780354, 780343Y, 780344Y, 780353Y, and 780354Y) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for device production.
Page 42: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List (1) Port pins (1/2) Pin Name Function After Reset Alternate Function Port 0 Input INTP0 8-bit I/O port INTP1 Input/output mode can be specified in 1-bit units. INTP2 An on-chip pull-up resistor can be used by setting software. INTP3/ADTRG INTP4 INTP5/PCL...
Page 43 CHAPTER 2 PIN FUNCTIONS (1) Port pins (2/2) Pin Name Function After Reset Alternate Function P70 to P73 Port 7 Input — 4-bit middle-voltage N-ch open-drain I/O port Input/output mode can be specified in 1-bit units. LEDs can be driven directly. On-chip pull-up resistor can be specified by mask option (mask ROM version only).
Page 44 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/2) Pin Name Function After Reset Alternate Function INTP0 Input External interrupt request input with specifiable valid edges Input (rising edge, falling edge, both rising and falling edges) INTP1 INTP2 INTP3 P03/ADTRG INTP4 INTP5 P05/PCL INTP6...
Page 45 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (2/2) Pin Name Function After Reset Alternate Function S0 to S11 Output LCD controller/driver segment signal output Output — (Static and dynamic display can be selected) S12 to S19 LCD controller/driver segment signal output P80 to P87 (for dynamic display) S20 to S27...
Page 46: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P07 (Port 0) These are 8-bit I/O ports. Besides serving as I/O ports, they function as an external interrupt request input, A/ D converter external trigger input, clock output, and timer I/O function. The following operation modes can be specified in 1-bit units.
Page 47: P20 To P27 (Port 2)
CHAPTER 2 PIN FUNCTIONS 2.2.3 P20 to P27 (Port 2) These are 8-bit I/O ports. Besides serving as I/O ports, they function as serial interface data I/O and clock I/O. The following operation modes can be specified in 1-bit units. (1) Port mode These ports function as 8-bit I/O ports.
Page 48: P40 To P43 (Port 4)
CHAPTER 2 PIN FUNCTIONS (e) TI50 and TI51 External count clock input pins to 8-bit timer/event counters 50 and 51. (f) TO00, TO50, and TO51 Timer output pins. 2.2.5 P40 to P43 (Port 4) These are 4-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode register 4 (PM4).
Page 49: P100 To P107 (Port 10)
CHAPTER 2 PIN FUNCTIONS 2.2.9 P100 to P107 (Port 10) These are 8-bit I/O ports. Besides serving as I/O ports, they function as segment signal output (for dynamic display) of the LCD controller/driver. Either the I/O port or segment signal output function can be selected by setting the pin function switching register 10 (PF10).
Page 50: Scom0
CHAPTER 2 PIN FUNCTIONS 2.2.15 SCOM0 This is a common signal output pin (for static display) of the LCD controller/driver. 2.2.16 V to V These are the LCD driving voltage pins. Individually connect to capacitors (recommended value: 0.47 µ F) externally between V and GND, V and GND, V...
Page 51: Ic (Mask Rom Version Only)
CHAPTER 2 PIN FUNCTIONS 2.2.24 IC (mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the µ PD780344, 780354, 780344Y, 780354Y Subseries at delivery. Connect it directly to the V or V pin with the shortest possible wire in the normal operation mode.
Page 52: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-1 shows the types of pin I/O circuit and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-1.
Page 53 CHAPTER 2 PIN FUNCTIONS Table 2-1. Pin I/O Circuit Types (2/2) Pin Name I/O Circuit Recommended Connection of Unused Pins Type COM0 to COM3 18-B Output Leave open. SCOM0 to V — — CAPH, CAPL RESET Input — Input Directly connect to V or V —...
Page 54 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 5-H Pullup P-ch enable Data P-ch IN/OUT Output N-ch disable Schmitt-triggered input with hysteresis characteristics Input enable Type 13-P Type 8-C IN/OUT Pullup Data P-ch N-ch enable Output disable Data...
Page 55 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 13-S Type 16   Mask   option   Feedback IN/OUT cut-off Data N-ch Output disable P-ch Type 17-D Type 17-G Data P-ch IN/OUT Output N-ch disable P-ch Input...
Page 56: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Spaces The µ PD780344, 780354, 780344Y, 780354Y Subseries can each access a 64 KB memory space. Figures 3-1 to 3-3 show the memory maps. Caution In the case of the internal memory capacity, the initial values of the memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all products ( µ...
Page 57 CHAPTER 3 CPU ARCHITECTURE (1) µ PD780343, 780353, 780343Y, 780353Y Set the value of the memory size switching register (IMS) to 46H, and the value of the internal expansion RAM size switching register (IXS) to 0BH (default setting: IMS = CFH, IXS = 0CH). Figure 3-1.
Page 58 CHAPTER 3 CPU ARCHITECTURE (2) µ PD780344, 780354, 780344Y, 780354Y Set the value of the memory size switching register (IMS) to 48H, and the value of the internal expansion RAM size switching register (IXS) to 0BH (default setting: IMS = CFH, IXS = 0CH). Figure 3-2.
Page 59 CHAPTER 3 CPU ARCHITECTURE (3) µ PD78F0354, 78F0354Y Set the value of the memory size switching register (IMS) to C8H or the value corresponding to the mask ROM version, and the value of the internal expansion RAM size switching register (IXS) to 0BH (default setting: IMS = CFH, IXS = 0CH).
Page 60: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space contains the program and table data. Normally, it is addressed with the program counter (PC). The µ PD780344, 780354, 780344Y, and 780354Y Subseries products incorporate an internal ROM (or flash memory), as listed below.
Page 61: Internal Data Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space The µ PD780344, 780354, 780344Y, and 780354Y Subseries products incorporate the following RAM. (1) Internal high-speed RAM The internal high-speed RAM is assigned to the area FD00H to FEFFH (512 bytes) of the mask ROM version and to the area FB00H to FEFFH (1,024 bytes) of the flash memory version.
Page 62: Data Memory Addressing
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the µ...
Page 63 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Correspondence Between Data Memory and Addressing ( µ PD780344, 780354, 780344Y, 780354Y) F F F F H Special function registers (SFRs) 256 × 8 bits SFR addressing F F 2 0 H F F 1 F H F F 0 0 H F E F F H General-purpose...
Page 64 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Correspondence Between Data Memory and Addressing ( µ PD78F0354, 78F0354Y) F F F F H Special function registers (SFRs) 256 × 8 bits SFR addressing F F 2 0 H F F 1 F H F F 0 0 H F E F F H General-purpose...
Page 65: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The µ PD780344, 780354, 780344Y, and 780354Y Subseries products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 66 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledgement operations of the CPU. When 0, the IE is set to the disable interrupt (DI) state, and only non-maskable interrupt request becomes acknowledgeable. Other interrupt requests are all disabled. When 1, the IE is set to the enable interrupt (EI) state and interrupt request acknowledgement enable is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority specification flag.
Page 67 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data To Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H FEDFH Register pair upper FEDEH FEDEH Register pair lower (b) CALL, CALLF, and CALLT instructions (when SP = FEE0H) FEE0H FEE0H FEDFH...
Page 68 CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Data To Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H FEDFH Register pair upper FEDEH FEDEH Register pair lower (b) RET instruction (when SP = FEDEH) FEE0H FEE0H FEDFH PC15 to PC8...
Page 69: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. They consist of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE, and HL).
Page 70: Special-Function Registers (Sfr)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special-function registers (SFR) Unlike a general-purpose register, each special function register has a special functions. They are allocated to the FF00H to FFFFH area. The special function registers can be manipulated like general-purpose registers, with operation, transfer and bit manipulation instructions.
Page 71 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Register List (1/3) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ FF00H Port 0 — √ √ FF01H Port 1 —...
Page 72 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Register List (2/3) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ FF30H Pull-up resistor option register 0 — √ √ FF32H Pull-up resistor option register 2 —...
Page 73 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Register List (3/3) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ FF90H LCD display mode register 3 LCDM3 — √ FF91H LCD clock control register 3 LCDC3...
Page 74: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 75: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
Page 76 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
Page 77: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] User’s Manual U15798EJ2V0UD...
Page 78: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general-purpose register is automatically (implicitly) addressed.
Page 79: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register specify code (Rn and RPn) of an instruction word in the registered bank specified with the register bank select flag (RBS0 and RBS1). Register addressing is carried out when an instruction with the following operand format is executed.
Page 80: Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code...
Page 81: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. An internal RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 82: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 83: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified with a register pair specify code in an instruction word of the register bank specified with a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory to be manipulated.
Page 84: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flag (RBS0 and RBS1) and the sum is used to address the memory.
Page 85: Based Indexed Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flag (RBS0 and RBS1) and the sum is used to address the memory.
Page 86: Stack Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. Stack addressing enables to address the internal high-speed RAM area only.
Page 87: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD780344, 780354, 780344Y, and 780354Y Subseries products incorporate ports as shown in Figure 4-1. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also serve as on-chip hardware I/O pins.
Page 88 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Name Pin Name Function Port 0 P00 to P07 I/O port. Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be used in 1-bit units by setting pull-up resistor option register 0 (PU0).
Page 89: Port Configuration
CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration A port consists of the following hardware. Table 4-2. Port Configuration Item Configuration Control registers Port mode register (PMm: m = 0, 2 to 4, 8 to 11) Pull-up resistor option register (PUm: m = 0, 2 to 4) Memory expansion register (MEM) Pin function switching registers (PF8 to PF11) Port...
Page 90 CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P00 to P04 PU00 to PU04 P-ch Alternate function PORT P00/INTP0, P01/INTP1, Output latch P02/INTP2, (P00 to P04) P03/INTP3/ADTRG, P04/INTP4 PM00 to PM04 PU: Pull-up resistor option register PM: Port mode register RD: Port 0 read signal WR: Port 0 write signal User’s Manual U15798EJ2V0UD...
Page 91 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P05 to P07 PU05 to PU07 P-ch Alternate function PORT Output latch P05/INTP5/PCL, (P05 to P07) P06/INTP6/TOB0, P07/TOA0/TMIB0 PM05 to PM07 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 0 read signal WR: Port 0 write signal User’s Manual U15798EJ2V0UD...
Page 92: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit input-only port. This port can also be used for A/D converter analog input. Figure 4-4 shows a block diagram of port 1. Figure 4-4. Block Diagram of P10 to P17 A/D converter P10/ANI0 to P17/ANI7 RD: Port 1 read signal...
Page 93: Port 2
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an 8-bit I/O port with an output latch. The P20 to P27 pins can be set to input mode/output mode in 1- bit units using port mode register 2 (PM2). An on-chip pull-up resistor can be used for the P20 to P27 pins in 1-bit units using pull-up resistor option register 2 (PU2).
Page 94 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P21, P24, P27 PU21, PU24, PU27 P-ch Selector PORT Output latch P21/SO3, (P21, P24, P27) P24/SO1, P27/TxD0 PM21, PM24, PM27 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal User’s Manual U15798EJ2V0UD...
Page 95 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P22, P25 PUB2 PU22, PU25 P-ch Alternate function PORT Output latch P22/SCK3, (P22, P25) P25/SCK1 PM22, PM25 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal User’s Manual U15798EJ2V0UD...
Page 96: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is a 6-bit I/O port with an output latch. The P30 to P35 pins can be set to input mode/output mode in 1- bit units using port mode register 3 (PM3). The P30 and P31 pins are 5 V N-ch open-drain.
Page 97 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P30, P31 (a) µ PD780344, 780354 Subseries Mask option resistor   Mask ROM version only.   No pull-up resistor for   flash memory version.   Selector PORT Output latch P30, P31 (P30, P31)
Page 98 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P32 to P34 PU32 to PU34 P-ch Alternate function PORT Output latch P32/TI51/TO51, (P32 to P34) P33/TI50/TO50, P34/TI01/TO00 PM32 to PM34 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 3 read signal WR: Port 3 write signal User’s Manual U15798EJ2V0UD...
Page 99 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P35 PU35 P-ch Alternate function PORT Output latch P35/TI00 (P35) PM35 PU: Pull-up resistor option register PM: Port mode register RD: Port 3 read signal WR: Port 3 write signal User’s Manual U15798EJ2V0UD...
Page 100: Port 4
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 Port 4 is a 4-bit I/O port with an output latch. The P40 to P43 pins can be set to input mode/output mode in 1- bit units using port mode register 4 (PM4). At the falling edge of any of the P40 to P43 pins, the interrupt request flag (KRIF) can be set to 1.
Page 101: Port 7
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 7 Port 7 is a 4-bit I/O port with an output latch. The P70 to P73 pins can be set to input mode/output mode in 1- bit units using port mode register 7 (PM7). In mask ROM versions use of a pull-up resistor can be set by mask option. The P70 to P73 pins can drive LEDs directly.
Page 102: Port
CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 8 Port 8 is an 8-bit I/O port with an output latch. The P80 to P87 pins can be set to input mode/output mode in 1- bit units using port mode register 8 (PM8). This port can also be used for LCD controller/driver segment output.
Page 103: Port 9
CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 9 Port 9 is an 8-bit I/O port with an output latch. The P90 to P97 pins can be set to input mode/output mode in 1- bit units using port mode register 9 (PM9). This port can also be used for LCD controller/driver segment output.
Page 104: Port 10
CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 10 Port 10 is an 8-bit I/O port with an output latch. The P100 to P107 pins can be set to input mode/output mode in 1-bit units using port mode register 10 (PM10). This port can also be used for LCD controller/driver segment output. This port can switched between an I/O port and a segment output port in 1-bit units by pin function switching register 10 (PF10).
Page 105: Port 11
CHAPTER 4 PORT FUNCTIONS 4.2.10 Port 11 Port 11 is a 4-bit I/O port with an output latch. P110 to P113 pins can be set to input mode/output mode in 1-bit units using port mode register 11 (PM11). This port can also be used for LCD controller/driver segment output. This port can be switched between an I/O port and a segment output port in 1-bit units by pin function switching register 11 (PF11).
Page 106: Port Function Control Registers
CHAPTER 4 PORT FUNCTIONS 4.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0, PM2 to PM4, PM7 to PM11) • Pull-up resistor option registers (PU0, PU2 to PU4) • Memory expansion register (MEM) •...
Page 107 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Format of Port Mode Registers (PM0, PM2 to PM4, PM7 to PM11) Address: FF20H After reset: FFH Symbol PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 Address: FF22H After reset: FFH Symbol PM27 PM26 PM25 PM24 PM23...
Page 108 CHAPTER 4 PORT FUNCTIONS (2) Pull-up resistor option registers (PU0, PU2 to PU4) These registers are used to set whether to use an on-chip pull-up resistor at each port or not in 1-bit units. By setting PU0 and PU2 to PU4, the on-chip pull-up resistors of the port pins corresponding to the bits in PU0 and PU2 to PU4 can be used.
Page 109 CHAPTER 4 PORT FUNCTIONS (3) Memory expansion mode register (MEM) This register is used to set whether port 4 is used as port pins or key input pins. MEM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 4-20.
Page 110 CHAPTER 4 PORT FUNCTIONS (4) Pin function switching registers (PF8 to PF11) These registers are used to select if ports 8 to 11 are used as port pins or segment pins in 1-bit units. PF8 to PF11 are set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the values of these registers to 00H.
Page 111: Port Function Operations
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 112: Selection Of Mask Option
CHAPTER 4 PORT FUNCTIONS 4.5 Selection of Mask Option The following mask option is provided in the mask ROM version. The flash memory versions have no mask options. Note that the mask option differs between the µ PD780344 and 780354 Subseries, and the µ PD780344Y and 780354Y Subseries.
Page 113: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 2 to 10 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC).
Page 114 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Clock Generator Block Diagram Subclock select ×4 register (SSCK) multiplication circuit Selector Timer 51, Subsystem watch timer, clock clock output function oscillator LCD controller/driver Prescaler Clock to peripheral Main system hardware clock Prescaler oscillator Standby Wait CPU clock...
Page 115: Clock Generator Control Registers
CHAPTER 5 CLOCK GENERATOR 5.3 Clock Generator Control Registers The clock generator is controlled by the following two registers. • Processor clock control register (PCC) • Subclock select register (SSCK) (1) Processor clock control register (PCC) The clock generator is controlled by the processor clock control register (PCC). PCC sets the CPU clock selection, the division ratio, main system clock oscillator operation/stop and whether Note to use the subsystem clock oscillator internal feedback resistor...
Page 116 CHAPTER 5 CLOCK GENERATOR Figure 5-3. Format of Processor Clock Control Register (PCC) Note 1 Address: FFFBH After reset: 04H Symbol PCC2 PCC1 PCC0 Note 2 Main system clock oscillation control Oscillation possible Oscillation stopped Subsystem clock feedback resistor selection Internal feedback resistor used Note 3 Internal feedback resistor not used...
Page 117 CHAPTER 5 CLOCK GENERATOR The fastest instructions of µ PD780344, 780354, 780344Y, and 780354Y Subseries are carried out in two CPU clocks. The relationship of the CPU clock (f ) and the minimum instruction execution time is shown in Table 5-2. Table 5-2.
Page 118: System Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (10 MHz TYP.) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an inverted-phase clock signal to the X2 pin.
Page 119: Subsystem Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (32.768 kHz TYP.) connected to the XT1 and XT2 pins. External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the XT1 pin and an inverted-phase clock signal to the XT2 pin.
Page 120: Examples Of Incorrect Resonator Connection
CHAPTER 5 CLOCK GENERATOR 5.4.3 Examples of incorrect resonator connection Figure 5-7 shows examples of incorrect resonator connection. Figure 5-7. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORTn (n = 0 to 7) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A, B, and...
Page 121: Divider
CHAPTER 5 CLOCK GENERATOR Figure 5-7. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Caution When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunction.
Page 122: Clock Generator Operations
CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operation mode including the standby mode. • Main system clock • Subsystem clock • CPU clock • Clock to peripheral hardware The following clock generator functions and operations are determined by using the processor clock control register (PCC).
Page 123: Main System Clock Operations
CHAPTER 5 CLOCK GENERATOR 5.5.1 Main system clock operations When the system operates on the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by setting PCC. (a) Because the operation guaranteed instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of PCC.
Page 124: Subsystem Clock Operations
CHAPTER 5 CLOCK GENERATOR 5.5.2 Subsystem clock operations When the system operates on the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out. (a) The minimum instruction execution time is either of the following, depending on the setting of the subclock select register (SSCK).
Page 125: Changing System Clock And Cpu Clock Settings
CHAPTER 5 CLOCK GENERATOR 5.6 Changing System Clock and CPU Clock Settings 5.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC).
Page 126: System Clock And Cpu Clock Switching Procedure
CHAPTER 5 CLOCK GENERATOR 5.6.2 System clock and CPU clock switching procedure This section describes the procedure for switching between the system clock and CPU clock. Figure 5-9. System Clock and CPU Clock Switching RESET Interrupt request signal System clock CPU clock Lowest- Highest-...
Page 127: Chapter 6 16-Bit Timer/Event Counter 0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.1 Outline of 16-Bit Timer/Event Counter 0 16-bit timer/event counter 0 can be used as an interval timer, PPG output, pulse width measurement (infrared ray remote control receive function), external event counter, or square wave output of any frequency. 6.2 Functions of 16-Bit Timer/Event Counter 0 16-bit timer/event counter 0 has the following functions.
Page 128: Configuration Of 16-Bit Timer/Event Counter 0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.3 Configuration of 16-Bit Timer/Event Counter 0 16-bit timer/event counter 0 consists of the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 0 Item Configuration 16 bits × 1 (TM0) Timer/counter 16-bit timer capture/compare register: 16 bits × 2 (CR00, CR01) Register Timer output 1 (TO00)
Page 129 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (1) 16-bit timer counter 0 (TM0) TM0 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read.
Page 130 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 CR00 is set by a 16-bit memory manipulation instruction. RESET input makes the value of this register undefined. Cautions 1. In the clear & start mode entered on a match between TM0 and CR00, set a value other than 0000H in CR00.
Page 131: Registers To Control 16-Bit Timer/Event Counter 0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.4 Registers to Control 16-Bit Timer/Event Counter 0 The following five registers are used to control 16-bit timer/event counter 0. • 16-bit timer mode control register 0 (TMC0) • Capture/compare control register 0 (CRC0) •...
Page 132 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-2. Format of 16-Bit Timer Mode Control Register 0 (TMC0) Address: FF60H After reset: 00H Symbol TMC0 TMC03 TMC02 OVF0 TMC03 TMC02 Operation mode and TO00 output timing selection Interrupt request generation clear mode selection Operation stop No change Not generated...
Page 133 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (2) Capture/compare control register 0 (CRC0) This register controls the operation of 16-bit timer capture/compare registers 00 and 01 (CR00, CR01). CRC0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 6-3.
Page 134 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (3) 16-bit timer output control register 0 (TOC0) This register controls the operation of the 16-bit timer/event counter 0 output controller. It sets R-S type flip-flop (LV0) setting/resetting, output inversion enabling/disabling, and 16-bit timer/event counter 0 timer output enabling/disabling.
Page 135 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (4) Prescaler mode register 0 (PRM0) This register is used to set the 16-bit timer counter 0 (TM0) count clock and TI00, TI01 input valid edges. PRM0 is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H.
Page 136 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P34/TI01/TO00 pin for timer output, set PM30 and the output latch of P30 to 0. PM3 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to FFH.
Page 137: Operations Of 16-Bit Timer/Event Counter 0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.5 Operations of 16-Bit Timer/Event Counter 0 6.5.1 Interval timer operations Setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 6-7 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value set in 16-bit timer capture/compare register 00 (CR00) beforehand as the interval.
Page 138 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-8. Interval Timer Configuration Diagram 16-bit timer capture/compare register 00 (CR00) INTTM00 16-bit timer counter 0 OVF0 (TM0) Noise TI00/P35 eliminator Clear circuit Figure 6-9. Timing of Interval Timer Operation Count clock TM0 count value 0000H 0001H 0000H 0001H...
Page 139: Ppg Output Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.5.2 PPG output operations Setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 6-10 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output operation, square waves are output from the TO00/TI01/P34 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16-bit timer capture/compare register 01 (CR01) and in 16-bit timer capture/compare register 00 (CR00), respectively.
Page 140 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-11. Configuration of PPG Output 16-bit timer capture/compare register 00 (CR00) Clear 16-bit timer counter 0 circuit (TM0) Noise TI00/P35 eliminator TO00/TI01/P34 16-bit timer capture/compare register 01 (CR01) Figure 6-12. PPG Output Operation Timing Count clock TM0 count value 0000H...
Page 141: Pulse Width Measurement Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.5.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/P35 pin and TI01/TO00/P34 pin using 16-bit timer counter 0 (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00/P35 pin.
Page 142 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-14. Configuration Diagram for Pulse Width Measurement by Free-Running Counter OVF0 16-bit timer counter 0 (TM0) 16-bit timer capture/compare TI00/P35 register 01 (CR01) INTTM01 Internal bus Figure 6-15. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) Count clock 0000H...
Page 143 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 6-16), it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/P35 pin and the TI01/ TO00/P34 pin.
Page 144 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 • Capture operation (free-running mode) Capture register operation in capture trigger input is shown. Figure 6-17. Capture Operation of CR01 with Rising Edge Specified Count clock n – 3 n – 2 n – 1 n + 1 TI00 Rising edge detection...
Page 145 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 6-19), it is possible to measure the pulse width of the signal input to the TI00/P35 pin. When the edge specified by bits 4 and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0) is input to the TI00/P35 pin, the value of TM0 is taken into 16-bit timer capture/compare register 01 (CR01) and an interrupt request signal (INTTM01) is set.
Page 146 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-20. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM0 count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 TI00 pin input CR01 capture value...
Page 147 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-21. Control Register Settings for Pulse Width Measurement by Means of Restart (a) 16-bit timer mode control register 0 (TMC0) TMC03 TMC02 OVF0 TMC0 Clears and starts at valid edge of TI00/P35 pin. (b) Capture/compare control register 0 (CRC0) CRC02 CRC01...
Page 148: External Event Counter Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.5.4 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/P35 pin with 16- bit timer counter 0 (TM0). TM0 is incremented each time the valid edge specified with prescaler mode register 0 (PRM0) is input. When the TM0 counted value matches the 16-bit timer capture/compare register 00 (CR00) value, TM0 is cleared to 0 and the interrupt request signal (INTTM00) is generated.
Page 149: Square-Wave Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-24. External Event Counter Configuration Diagram 16-bit timer capture/compare register 00 (CR00) Match INTTM00 Clear 16-bit timer counter 0 (TM0) OVF0 Noise eliminator 16-bit timer capture/compare Valid edge of TI00 Noise eliminator register 01 (CR01) Internal bus Figure 6-25.
Page 150 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-26. Control Register Settings in Square-Wave Output Mode (a) 16-bit timer mode control register 0 (TMC0) TMC03 TMC02 OVF0 TMC0 Clears and starts on match between TM0 and CR00. (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00...
Page 151: 16-Bit Timer/Event Counter 0 Cautions
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.6 16-Bit Timer/Event Counter 0 Cautions (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 0 (TM0) is started asynchronously to the count clock. Figure 6-28.
Page 152 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (4) Capture register data retention timings If the valid edge of the TI00/P35 pin is input during 16-bit timer capture/compare register 01 (CR01) read, CR01 carries out a capture operation but the read value at this time is not guaranteed. However, the interrupt request signal (INTTM01) is generated upon detection of the valid edge.
Page 153 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (6) Operation of OVF0 flag <1> The OVF0 flag is set to 1 in the following case. Select any of the clear & start mode entered on a match between TM0 and CR00, the mode in which the timer is cleared and started by the valid edge of TI00, and the free-running mode.
Page 154 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (8) Timer operation <1> Even if 16-bit timer counter 0 (TM0) is read, the value is not captured by 16-bit timer capture/compare register 01 (CR01). <2> Regardless of the CPU’s operation mode, when the timer stops, the signals input to pins TI00/TI01 are not acknowledged.
Page 155 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (11) Edge detection <1> If the TI00 pin or the TI01 pin is high level immediately after system reset and the rising edge or both the rising and falling edges are specified as the valid edge for the TI00 pin or TI01 pin to enable 16-bit timer counter 0 (TM0) operation, a rising edge is detected immediately.
Page 156: Chapter 7 8-Bit Timers A0, B0
CHAPTER 7 8-BIT TIMERS A0, B0 7.1 8-Bit Timer A0, B0 Functions The µ PD780344, 780354, 780344Y, 780354Y Subseries have 8-bit timer A0 and 8-bit timer/event counter B0. The operation modes listed in the following table can be set via mode register settings. Table 7-1.
Page 157: 8-Bit Timer A0, B0 Configuration
CHAPTER 7 8-BIT TIMERS A0, B0 7.2 8-Bit Timer A0, B0 Configuration 8-bit timer A0 and B0 consist of the following hardware. Table 7-2. Configuration of 8-Bit Timer A0, B0 Item Configuration 8 bits × 2 (TMA0, TMB0) Timer counters Compare registers: 8 bits ×...
Page 158 Internal bus 8-bit timer mode control register A0 (TMCA0) TCEA0 TCLA01 TCLA00 TMDA00 TOEA0 PM07 output latch 8-bit compare Decoder register A0 (CRA0) Selector Match TOA0/P07/ TMIB0 Bit 7 of TMB0 (from Figure 7-2 (A)) 8-bit timer counter A0 (TMA0) Clear Timer B0 interrupt request signal (from Figure 7-2 (B))
Page 159 Internal bus Carrier generator output 8-bit timer mode control control register B0 (TCAB0) register B0 (TMCB0) 8-bit H-width compare 8-bit compare TCEB0 TCLB02 TCLB01 TCLB00 TMDB01 TMDB00 TOEB0 register B0 (CRHB0) register B0 (CRB0) RMCB0 NRZBB0 NRZB0 Decoder From Figure 7-1 (G) Selector Timer A0 match signal (during carrier generator mode)
Page 160 CHAPTER 7 8-BIT TIMERS A0, B0 Figure 7-3. Block Diagram of Output Controller (Timer B0) RMCB0 TOEB0 NRZB0 output latch PM06 TOB0/INTP6/P06 Carrier clock (in carrier generator mode) or timer B0 output signal (in other than carrier generator mode) Carrier generator mode (1) 8-bit compare register A0 (CRA0) This 8-bit register is used to continually compare the value set to CRA0 with the count value in 8-bit timer counter A0 (TMA0) and to generate an interrupt request (INTTMA0) when a match occurs.
Page 161 CHAPTER 7 8-BIT TIMERS A0, B0 (4) 8-bit timer counters A0 and B0 (TMA0 and TMB0) These are 8-bit registers that are used to count the count pulse. TMA0 and TMB0 are read by an 8-bit memory manipulation instruction. RESET input sets TMA0 and TMB0 to 00H. TMA0 and TMB0 are cleared to 00H under the following conditions.
Page 162: Registers To Control 8-Bit Timer A0, B0
CHAPTER 7 8-BIT TIMERS A0, B0 7.3 Registers to Control 8-Bit Timer A0, B0 8-bit timer A0 and B0 are controlled by the following four registers. • 8-bit timer mode control register A0 (TMCA0) • 8-bit timer mode control register B0 (TMCB0) •...
Page 163 CHAPTER 7 8-BIT TIMERS A0, B0 (1) 8-bit timer mode control register A0 (TMCA0) 8-bit timer mode control register A0 (TMCA0) is used to control the timer A0 count clock setting and the operation mode setting. TMCA0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMCA0 to 00H.
Page 164 CHAPTER 7 8-BIT TIMERS A0, B0 (2) 8-bit timer mode control register B0 (TMCB0) 8-bit timer mode control register B0 (TMCB0) is used to control the timer B0 count clock setting and the operation mode setting. TMCB0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMCB0 to 00H.
Page 165 CHAPTER 7 8-BIT TIMERS A0, B0 (3) Carrier generator output control register B0 (TCAB0) This register is used to set the timer output data during carrier generator mode. TCAB0 is set by an 8-bit memory manipulation instruction. RESET input sets TCAB0 to 00H. Figure 7-6.
Page 166: 8-Bit Timer A0, B0 Operation
CHAPTER 7 8-BIT TIMERS A0, B0 7.4 8-Bit Timer A0, B0 Operation 7.4.1 Operation as 8-bit timer counter Timer A0 and timer B0 can independently be used as an 8-bit timer counter. The following modes can be used for the 8-bit timer counter. •...
Page 167 CHAPTER 7 8-BIT TIMERS A0, B0 Table 7-3. Interval Time of Timer A0 TCLA01 TCLA00 Minimum Interval Time Maximum Interval Time Resolution (1.6 µ s) (410 µ s) (1.6 µ s) (6.4 µ s) (6.4 µ s) (1.64 ms) Input cycle of timer B0 Input cycle of timer B0 Input cycle of timer B0 match signal ×...
Page 168 CHAPTER 7 8-BIT TIMERS A0, B0 Figure 7-9. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to 00H) Count clock TMn0 CRn0 TCEn0 Count start INTTMn0 TOn0 Remark n = A, B Figure 7-10. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH) Count clock TMn0 Clear...
Page 169 CHAPTER 7 8-BIT TIMERS A0, B0 Figure 7-11. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N < M)) Count clock TMn0 Clear Clear Clear CRn0 TCEn0 Count start INTTMn0 Interrupt acknowledgement Interrupt acknowledgement TOn0 CRn0 overwritten Remarks 1.
Page 170 CHAPTER 7 8-BIT TIMERS A0, B0 Figure 7-13. Timing of Interval Timer Operation with 8-Bit Resolution (When Timer B0 Match Signal Is Selected for Timer A0 Count Clock) Timer B0 count clock TMB0 Clear Clear Clear Clear CRB0 TCEB0 Count start INTTMB0 Input clock to timer A0 (timer B0 match signal)
Page 171 CHAPTER 7 8-BIT TIMERS A0, B0 (2) Operation as external event counter with 8-bit resolution (timer B0 only) The external event counter counts the number of external clock pulses input to the TMIB0/P07/TOA0 pin by using 8-bit timer counter B0 (TMB0). To operate timer B0 as an external event counter, settings must be made in the following sequence.
Page 172 CHAPTER 7 8-BIT TIMERS A0, B0 (3) Operation as square-wave output with 8-bit resolution Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register n0 (CRn0). To operate timer n0 for square-wave output, settings must be made in the following sequence. <1>...
Page 173 CHAPTER 7 8-BIT TIMERS A0, B0 Figure 7-15. Timing of Square-Wave Output with 8-Bit Resolution Count clock TMn0 Clear Clear Clear CRn0 TCEn0 Count start INTTMn0 Interrupt acknowledgement Interrupt acknowledgement Interrupt acknowledgement Note TOn0 Square-wave output cycle Note The initial value of TOn0 is low level when output is enabled (TOEn0 = 1). Remarks 1.
Page 174: Operation As 16-Bit Timer Counter
CHAPTER 7 8-BIT TIMERS A0, B0 7.4.2 Operation as 16-bit timer counter Timer A0 and timer B0 can be used as a 16-bit timer counter using cascade connection. In this case, 8-bit timer counter A0 (TMA0) is the higher 8 bits and 8-bit timer counter B0 (TMB0) is the lower 8 bits. 8-bit timer B0 controls reset and clear.
Page 175 CHAPTER 7 8-BIT TIMERS A0, B0 Table 7-6. Interval Time with 16-Bit Resolution TCLB02 TCLB01 TCLB00 Minimum Interval Time Maximum Interval Time Resolution (0.4 µ s) (0.4 µ s) (26.2 ms) (0.8 µ s) (0.8 µ s) (52.4 ms) input cycle × 2 input cycle input cycle /2 input cycle ×...
Page 176 TMB0 count clock TMB0 count value FFH 00H 7FH 80H FFH 00H 7FH 80H FFH 00H Not cleared because TMA0 does not match Cleared because TMA0 and TMB0 match simultaneously CRB0 TCEB0 Count start TMA0 count clock X − 1 X −...
Page 177 CHAPTER 7 8-BIT TIMERS A0, B0 (2) Operation as external event counter with 16-bit resolution The external event counter counts the number of external clock pulses input to the TMIB0/P07/TOA0 pin by TMA0 and TMB0. To operate as an external event counter with 16-bit resolution, settings must be made in the following sequence. <1>...
Page 178 TMB0 count clock TMB0 count value FFH 00H 7FH 80H FFH 00H 7FH 80H FFH 00H Not cleared because TMA0 does not match Cleared because TMA0 and TMB0 match simultaneously CRB0 TCEB0 Count start TMA0 count clock X − 1 X −...
Page 179 CHAPTER 7 8-BIT TIMERS A0, B0 (3) Operation as square-wave output with 16-bit resolution Square waves of any frequency can be output at an interval specified by the count value preset in CRA0 and CRB0. To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1>...
Page 180 TMB0 count clock TMB0 count value FFH 00H 7FH 80H FFH 00H 7FH 80H FFH 00H Not cleared because TMA0 does not match Cleared because TMA0 and TMB0 match simultaneously CRB0 TCEB0 Count start TMA0 count clock X − 1 X −...
Page 181: Operation As Carrier Generator
CHAPTER 7 8-BIT TIMERS A0, B0 7.4.3 Operation as carrier generator An arbitrary carrier clock generated by TMB0 can be output in the cycle set in TMA0. To operate timer A0 and timer B0 as carrier generators, settings must be made in the following sequence. <1>...
Page 182 CHAPTER 7 8-BIT TIMERS A0, B0 Figure 7-19. Timing of Carrier Generator Operation (When CRB0 = N, CRHB0 = M (M > N)) TMB0 count clock TMB0 count value Clear Clear Clear Clear CRB0 CRHB0 TCEB0 Count start INTTMB0 Carrier clock TMA0 count clock TMA0...
Page 183 CHAPTER 7 8-BIT TIMERS A0, B0 Figure 7-20. Timing of Carrier Generator Operation (When CRB0 = N, CRHB0 = M (M < N)) TMB0 count clock TMB0 count value Clear Clear Clear Clear CRB0 CRHB0 TCEB0 Count start INTTMB0 Carrier clock TMA0 count clock TMA0...
Page 184 CHAPTER 7 8-BIT TIMERS A0, B0 Figure 7-21. Timing of Carrier Generator Operation (When CRB0 = CRHB0 = N) TMB0 count clock TMB0 count value Clear Clear Clear Clear Clear CRB0 CRHB0 TCEB0 Count start INTTMB0 Carrier clock TMA0 count clock TMA0 count value CRA0...
Page 185: Operation As Pwm Output (Timer B0 Only)
CHAPTER 7 8-BIT TIMERS A0, B0 7.4.4 Operation as PWM output (timer B0 only) In the PWM output mode, a pulse of any duty ratio can be output by setting a low-level width using CRB0 and a high-level width using CRHB0. To operate timer B0 in PWM output mode, settings must be made in the following sequence.
Page 186 CHAPTER 7 8-BIT TIMERS A0, B0 Figure 7-22. PWM Output Mode Timing (Basic Operation) TMB0 count clock TMB0 count value Clear Clear Clear Clear CRB0 CRHB0 TCEB0 Count start INTTMB0 Note TOB0 Note The initial value of TOB0 is low level when output is enabled (TOEB0 = 1). Remark N, M = 00H to FFH Figure 7-23.
Page 187: 8-Bit Timer A0, B0 Cautions
CHAPTER 7 8-BIT TIMERS A0, B0 7.5 8-Bit Timer A0, B0 Cautions (1) Error on starting timer An error of up to 1 clock is included in the time between the timer being started and a match signal being generated. This is because 8-bit timer counter n0 (TMn0) is started asynchronously to the count pulse.
Page 188: Chapter 8 8-Bit Timer/Event Counters 50, 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 8.1 Outline of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 can be used as an interval timer, an external event counter, to output square wave output with any selected frequency, and PWM output. 8.2 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions.
Page 189 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 8-1. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus 8-bit timer compare Selector INTTM50 register 50 (CR50) TI50/TO50/P33 Match 8-bit timer TO50/TI50/P33 counter 50 (TM50) Clear Invert level Selector TCE50 TMC506 LVS50 LVR50 TMC501 TOE50 TCL502 TCL501 TCL500 8-bit timer mode control Timer clock select...
Page 190: Configuration Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 8.3 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 consist of the following hardware. Table 8-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Configuration Timer register 8-bit timer counter 5n (TM5n) Register 8-bit timer compare register 5n (CR5n)
Page 191: Registers To Control 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 8.4 Registers to Control 8-Bit Timer/Event Counters 50 and 51 The following three types of registers are used to control 8-bit timer/event counters 50 and 51. • Timer clock select register 5n (TCL5n) •...
Page 192 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 8-4. Format of Timer Clock Select Register 51 (TCL51) Address: FF74H After reset: 00H Symbol TCL51 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 Count clock selection TI51 falling edge TI51 rising edge /2 (5 MHz) (1.25 MHz) (313 kHz) (78.1 kHz)
Page 193 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 8-5. Format of 8-Bit Timer Mode Control Register 5n (TMC5n) Address: FF70H (TMC50) FF73H (TMC51) After reset: 00H Symbol TMC5n TCE5n TMC5n6 LVS5n LVR5n TMC5n1 TOE5n TCE5n TM5n count operation control After clearing to 0, count operation disabled (prescaler disabled) Count operation start TMC5n6 TM5n operation mode selection...
Page 194 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 (3) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P33/TO50/TI50 and P32/TO51/TI51 pins for timer output, set PM33, PM32 and the output latches of P33 and P32 to 0. PM3 is set by a 1-bit or 8-bit memory manipulation instruction.
Page 195: Operation Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 8.5 Operation of 8-Bit Timer/Event Counters 50 and 51 8.5.1 Interval timer operation The 8-bit timer/event counters operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count values of 8-bit timer counter 5n (TM5n) match the values set to CR5n, counting continues with the TM5n values cleared to 0 and the interrupt request signals (INTTM5n) are generated.
Page 196 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 8-7. Interval Timer Operation Timings (2/3) (b) When CR5n = 00H Count clock TM5n CR5n TCE5n INTTM5n TO5n Interval time (c) When CR5n = FFH Count clock TM5n CR5n TCE5n INTTM5n Interrupt request Interrupt request acknowledged acknowledged...
Page 197 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 8-7. Interval Timer Operation Timings (3/3) (d) Operated by CR5n transition (M < N) Count clock TM5n CR5n TCE5n INTTM5n TO5n CR5n transition TM5n overflows since M < N (e) Operated by CR5n transition (M > N) Count clock TM5n N –...
Page 198: External Event Counter Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 8.5.2 External event counter operation The external event counter counts the number of external clock pulses to be input to TI5n by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock select register 5n (TCL5n) is input. Either the rising or falling edge can be selected.
Page 199: Square-Wave Output Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 8.5.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined according to the value preset to 8- bit timer compare register 5n (CR5n). The TO5n pin output status is reversed at intervals determined according to the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1.
Page 200: Pwm Output Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 8.5.4 PWM output operation The 8-bit timer/event counter operates as PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set to 1. The duty rate pulse determined by the value set to 8-bit timer compare register 5n (CR5n) is output from TO5n. Set the active level width of the PWM pulse to CR5n;...
Page 201 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 8-10. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H CR5n TCE5n INTTM5n TO5n Active level Inactive level...
Page 202 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 (2) Operated by CR5n transition Figure 8-11. Timing of Operation by CR5n Transition (a) CR5n value shifts from N to M before overflow of TM5n Count clock TM5n N N + 1 N + 2 FFH 00H 01H M M + 1 M + 2 FFH 00H 01H 02H...
Page 203: 8-Bit Timer/Event Counter 50 And 51 Cautions
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51 8.6 8-Bit Timer/Event Counter 50 and 51 Cautions (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counter 5n (TM5n) is started asynchronously to the count pulse.
Page 204: Chapter 9 Watch Timer
CHAPTER 9 WATCH TIMER 9.1 Outline of Watch Timer The watch timer generates interrupt requests (INTWTN0 and INTWTNI0) at the preset time interval. 9.2 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously.
Page 205 CHAPTER 9 WATCH TIMER (1) Watch timer By using the main system clock or subsystem clock, interrupt requests (INTWTN0) are generated at preset intervals. An interrupt request (INTWTN0) occurs at an interval of 0.5 second when using the 32.768 kHz subsystem clock. Also, an interrupt request (INTWTN0) can be generated at an interval of 1.0 seconds when using the 32.768 kHz subsystem clock via a setting in the watch timer interrupt time select register (WTIM).
Page 206: Watch Timer Configuration
CHAPTER 9 WATCH TIMER 9.3 Watch Timer Configuration The watch timer consists of the following hardware. Table 9-3. Watch Timer Configuration Item Configuration 11 bits × 1, 5 bits × 1 Prescaler Control register Watch timer operation mode register 0 (WTNM0) Watch timer interrupt time select register (WTIM) 9.4 Registers to Control Watch Timer The following two registers are used to control the watch timer.
Page 207 CHAPTER 9 WATCH TIMER Figure 9-2. Format of Watch Timer Operation Mode Register 0 (WTNM0) Address: FF41H After reset: 00H Symbol WTNM0 WTNM07 WTNM06 WTNM05 WTNM04 WTNM03 WTNM02 WTNM01 WTNM00 WTNM07 Watch timer count clock selection (39.1 kHz) Note (32.768 kHz) or f /2 (16.384 kHz) WTNM06 WTNM05...
Page 208 CHAPTER 9 WATCH TIMER (2) Watch timer interrupt time select register (WTIM) This register is used to set the interrupt time by selecting either the source clock or the clock divided by 2 for the subsystem clock to be input to the watch timer. WTIM is set by a 1-bit or 8-bit memory manipulation instruction.
Page 209: Watch Timer Operations
CHAPTER 9 WATCH TIMER 9.5 Watch Timer Operations 9.5.1 Watch timer operation By using the main system clock or subsystem clock, the watch timer operates as a watch timer with preset timing intervals. Bits 2, 3, and 7 (WTNM02, WTNM03, and WTNM07) of watch timer operation mode register 0 (WTNM0) enable the selection of the timing for the watch timer.
Page 210: Chapter 10 Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.1 Outline of Watchdog Timer The watchdog timer can also be used to generate a non-maskable interrupt request, maskable interrupt request, or RESET signal at the preset time intervals. 10.2 Watchdog Timer Functions The watchdog timer has the following functions. •...
Page 211 CHAPTER 10 WATCHDOG TIMER (1) Watchdog timer mode A program loop is detected. Upon detection of a program loop, a non-maskable interrupt request or RESET can be generated. Table 10-1. Watchdog Timer Program Loop Detection Time Program Loop Detection Time ×...
Page 212: Watchdog Timer Configuration
CHAPTER 10 WATCHDOG TIMER 10.3 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 10-3. Watchdog Timer Configuration Item Configuration Control registers Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) Oscillation stabilization time select register (OSTS) 10.4 Registers to Control Watchdog Timer The following three registers are used to control the watchdog timer.
Page 213 CHAPTER 10 WATCHDOG TIMER (1) Watchdog timer clock select register (WDCS) This register sets overflow time of the watchdog timer and the interval timer. WDCS is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 10-2.
Page 214 CHAPTER 10 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operation mode and enables/disables counting. WDTM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 10-3.
Page 215 CHAPTER 10 WATCHDOG TIMER (3) Oscillation stabilization time select register (OSTS) A register to select oscillation stabilization time from reset time or STOP mode released time to the time when oscillation is stabilized. OSTS is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 04H.
Page 216: Watchdog Timer Operations
CHAPTER 10 WATCHDOG TIMER 10.5 Watchdog Timer Operations 10.5.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect a program loop. The program loop detection time interval is selected with bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select register (WDCS).
Page 217: Interval Timer Operation
CHAPTER 10 WATCHDOG TIMER 10.5.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. The interval time of interval timer is selected with bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select register (WDCS).
Page 218: Chapter 11 Clock Output Controller
CHAPTER 11 CLOCK OUTPUT CONTROLLER 11.1 Outline of Clock Output Controller The clock output circuit supplies other devices with the divided main system clock and the subsystem clock. 11.2 Clock Output Controller Functions The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs.
Page 219: Configuration Of Clock Output Controller
CHAPTER 11 CLOCK OUTPUT CONTROLLER 11.3 Configuration of Clock Output Controller The clock output controller consists of the following hardware. Table 11-1. Configuration of Clock Output Controller Item Configuration Control registers Clock output select register (CKS) Note Port mode register 0 (PM0) Note See Figure 4-3 P05 to P07 Block Diagram.
Page 220 CHAPTER 11 CLOCK OUTPUT CONTROLLER Figure 11-2. Format of Clock Output Select Register (CKS) Address: FF40H After reset: 00H R/W Symbol CLOE CCS3 CCS2 CCS1 CCS0 CLOE PCL output enable/disable setting Stop clock division circuit operation. PCL fixed to low level Enable clock division circuit operation.
Page 221: Clock Output Controller Operations
CHAPTER 11 CLOCK OUTPUT CONTROLLER (2) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the PCL/INTP5/P05 pin for clock output, set PM05 and the output latch of P05 to 0. PM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to FFH.
Page 222: Chapter 12 8-Bit A/D Converter ( Μ Pd780344, 780344Y Subseries)
CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) 12.1 8-Bit A/D Converter Functions The 8-bit A/D converter is an 8-bit resolution converter that converts analog inputs into digital values. It can control up to 8 analog input channels (ANI0 to ANI7). (1) Hardware start Conversion is started by trigger input (ADTRG: rising edge, falling edge, or both rising and falling edges can be specified).
Page 223 CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) Figure 12-1. 8-Bit A/D Converter Block Diagram Series resistor string ANI0/P10 Sample & hold circuit ANI1/P11 ANI2/P12 Voltage comparator ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Successive approximation register (SAR) Edge ADTRG/INTP3/P03 detector Controller INTAD0...
Page 224: 8-Bit A/D Converter Configuration
CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) 12.2 8-Bit A/D Converter Configuration The 8-bit A/D converter consists of the following hardware. Table 12-1. 8-Bit A/D Converter Configuration Item Configuration Analog input 8 channels (ANI0 to ANI7) Registers Successive approximation register (SAR) A/D conversion result register 1 (ADCR1) Control registers...
Page 225 CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) (6) ANI0 to ANI7 pins These are eight analog input pins used to input analog signals to undergo A/D conversion to the A/D converter. ANI0 to ANI7 are alternate-function pins that can also be used for digital inputs. Cautions 1.
Page 226: Registers To Control 8-Bit A/D Converter
CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) 12.3 Registers to Control 8-Bit A/D Converter The following two registers are used to control the 8-bit A/D converter. • A/D converter mode register 0 (ADM0) • Analog input channel specification register 0 (ADS0) (1) A/D converter mode register 0 (ADM0) This register sets the conversion time for the analog input to be A/D converted, conversion start/stop, and an external trigger.
Page 227 CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) Figure 12-2. Format of A/D Converter Mode Register 0 (ADM0) Address: FF80H After reset: 00H R/W Symbol ADM0 ADCS0 TRG0 FR02 FR01 FR00 EGA01 EGA00 ADCE0 ADCS0 A/D conversion operation control Stop conversion operation.
Page 228 CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) Table 12-2. Settings of ADCS0 and ADCE0 ADCS0 ADCE0 A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (only reference voltage generator consumes power) Note Conversion mode (reference voltage generator operation stopped Conversion mode (reference voltage generator operates)
Page 229 CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) (2) Analog input channel specification register 0 (ADS0) This register specifies the analog voltage input port for A/D conversion. ADS0 is set by an 8-bit memory manipulation instruction. RESET input sets ADS0 to 00H. Figure 12-4.
Page 230: 8-Bit A/D Converter Operations
CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) 12.4 8-Bit A/D Converter Operations 12.4.1 Basic operations of 8-bit A/D converter <1> Select one channel for A/D conversion using analog input channel specification register 0 (ADS0). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3>...
Page 231 CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) Figure 12-5. Basic Operation of 8-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR1 result INTAD0 A/D conversion operations are performed continuously until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software.
Page 232: Input Voltage And Conversion Results
CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) 12.4.2 Input voltage and conversion results The relationship between the analog voltage input to the analog input pins (ANI0 to ANI7) and the logical A/D conversion result (stored in A/D conversion result register 1 (ADCR1)) is shown by the following expression. ×...
Page 233: 8-Bit A/D Converter Operation Mode
CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) 12.4.3 8-bit A/D converter operation mode Select one analog input channel from among ANI0 to ANI7 using analog input channel specification register 0 (ADS0) to start A/D conversion. A/D conversion can be started in either of the following two ways. •...
Page 234 CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) Figure 12-7. A/D Conversion by Hardware Start (When Falling Edge Is Specified) ADTRG ADM0 set ADS0 rewrite ADCE0 = 1, ADCS0 = 1, TRG0 = 1 Standby Standby Standby A/D conversion ANIn ANIn ANIn...
Page 235 CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) (2) A/D conversion by software start When bit 6 (TRG0) and bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) are set to 0 and 1 after bit 0 (ADCE0) is set to 1, A/D conversion of the voltage applied to the analog input pin specified by analog input channel specification register 0 (ADS0) starts.
Page 236: How To Read A/D Converter Characteristics Table
CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) 12.5 How to Read A/D Converter Characteristics Table Here we will explain the special terms unique to A/D converters. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per 1 bit of digital output is called 1LSB (Least Significant Bit).
Page 237 CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) (4) Conversion time This expresses the time from when sampling is started to the time when the digital output was obtained. Sampling time is included in the conversion time in the characteristics table. (5) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample &...
Page 238: A/D Converter Cautions
CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) 12.6 A/D Converter Cautions (1) Power consumption in standby mode The A/D converter stops operating in the standby mode. At this time, the power consumption can be reduced by setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) to 0. Figure 12-11 shows the circuit configuration of the series resistor string.
Page 239 CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) (4) Noise countermeasures To maintain the 8-bit resolution, attention must be paid to noise input to the AV and ANI0 to ANI7 pins. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 12-12 to reduce noise.
Page 240 CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) (8) Interrupt request flag (ADIF0) The interrupt request flag (ADIF0) is not cleared even if analog input channel specification register 0 (ADS0) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ADS0 rewrite.
Page 241 CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) (11) Timing at which A/D conversion result is undefined The A/D conversion value may be undefined if the timing of completion of A/D conversion and the timing of stopping the A/D conversion conflict with each other. Therefore, read the A/D conversion result during the A/ D conversion operation.
Page 242 CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) (13) AV and AV pins Connect a capacitor between the AV and AV pins to minimize conversion errors due to noise. If an A/D conversion operation has been stopped and then is started, the voltage applied to the AV and AV pins becomes unstable, causing the accuracy of the A/D conversion to drop.
Page 243 CHAPTER 12 8-BIT A/D CONVERTER ( µ PD780344, 780344Y SUBSERIES) (15) Internal equivalent circuit of ANI0 to ANI7 pins and permissible signal source impedance To complete sampling within the sampling time with sufficient A/D conversion accuracy, the impedance of the signal source such as a sensor must be sufficiently low.
Page 244: Chapter 13 10-Bit A/D Converter ( Μ Pd780354, 780354Y Subseries)
CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) 13.1 10-Bit A/D Converter Functions The 10-bit A/D converter is a 10-bit resolution converter that converts analog inputs into digital signals. It can control up to 8 analog input channels (ANI0 to ANI7). (1) Hardware start Conversion is started by trigger input (ADTRG: rising edge, falling edge, or both rising and falling edges can be specified).
Page 245: 10-Bit A/D Converter Configuration
CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) 13.2 10-Bit A/D Converter Configuration 10-bit A/D converter consists of the following hardware. Table 13-1. 10-Bit A/D Converter Configuration Item Configuration Analog input 8 channels (ANI0 to ANI7) Registers Successive approximation register (SAR) A/D conversion result register 0 (ADCR0) Control registers A/D converter mode register 0 (ADM0)
Page 246: Registers To Control 10-Bit A/D Converter
CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) (6) ANI0 to ANI7 pins These are eight analog input pins used to input analog signals to undergo A/D conversion to the A/D converter. ANI0 to ANI7 can be used as input ports except for the pins specified as analog input by analog input channel specification register 0 (ADS0).
Page 247 CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) Figure 13-2. Format of A/D Converter Mode Register 0 (ADM0) Address: FF80H After reset: 00H R/W Symbol ADM0 ADCS0 TRG0 FR02 FR01 FR00 EGA01 EGA00 ADCE0 ADCS0 A/D conversion operation control Stop conversion operation.
Page 248 CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) Table 13-2. Settings of ADCS0 and ADCE0 ADCS0 ADCE0 A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (only reference voltage generator consumes power) Note Conversion mode (reference voltage generator operation stopped Conversion mode (reference voltage generator operates)
Page 249 CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) (2) Analog input channel specification register 0 (ADS0) This register specifies the analog voltage input port for A/D conversion. ADS0 is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 13-4.
Page 250: 10-Bit A/D Converter Operation
CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) 13.4 10-Bit A/D Converter Operation 13.4.1 Basic operations of 10-bit A/D converter <1> Select one channel for A/D conversion using analog input channel specification register 0 (ADS0). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3>...
Page 251 CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) Figure 13-5. Basic Operation of 10-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR0 result INTAD0 A/D conversion operations are performed continuously until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software.
Page 252: Input Voltage And Conversion Results
CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) 13.4.2 Input voltage and conversion results The relationship between the analog voltage input to the analog input pins (ANI0 to ANI7) and the logical A/D conversion result (stored in A/D conversion result register 0 (ADCR0)) is shown by the following expression. ×...
Page 253: 10-Bit A/D Converter Operation Mode
CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) 13.4.3 10-bit A/D converter operation mode Select one analog input channel from among ANI0 to ANI7 using analog input channel specification register 0 (ADS0) to start A/D conversion. A/D conversion can be started in either of the following two ways. •...
Page 254 CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) Figure 13-7. A/D Conversion by Hardware Start (When Falling Edge Is Specified) ADTRG ADM0 set ADS0 rewrite ADCE0 = 1, ADCS0 = 1, TRG0 = 1 Standby A/D conversion Standby state ANIn ANIn ANIn...
Page 255 CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) (2) A/D conversion by software start When bit 6 (TRG0) and bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) are set to 0 and 1 after bit 0 (ADCE0) is set to 1, A/D conversion of the voltage applied to the analog input pin specified by analog input channel specification register 0 (ADS0) starts.
Page 256: How To Read The A/D Converter Characteristics Table
CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) 13.5 How to Read the A/D Converter Characteristics Table Here we will explain the special terms unique to A/D converters. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per 1 bit of digital output is called 1LSB (Least Significant Bit).
Page 257 CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) (4) Zero-scale error This shows the difference between the actual measured value of the analog input voltage and the theoretical value (1/2 LSB) when the digital output changes from 0……000 to 0……001. If the actual measured value is greater than the theoretical value, it shows the difference between the actual measured value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0……001 to 0……010.
Page 258 CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) (8) Conversion time This expresses the time from when the sampling is started to the time when the digital output was obtained. Sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample and hold circuit.
Page 259: A/D Converter Cautions
CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) 13.6 A/D Converter Cautions (1) Power consumption in standby mode The A/D converter stops operating in the standby mode. At this time, the power consumption can be reduced by setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) to 0. Figure 13-15 shows the circuit configuration of the series resistor string.
Page 260 CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AV and ANI0 to ANI7 pins. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 13-16 to reduce noise.
Page 261 CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) (8) Interrupt request flag (ADIF0) The interrupt request flag (ADIF0) is not cleared even if analog input channel specification register 0 (ADS0) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ADS0 rewrite.
Page 262 CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) (11) Timing at which A/D conversion result is undefined The A/D conversion value may be undefined if the timing of completion of A/D conversion and the timing of stopping the A/D conversion conflict with each other. Therefore, read the A/D conversion result during the A/ D conversion operation.
Page 263 CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) (13) AV pin and AV pins Connect a capacitor to the AV and AV pins to minimize conversion errors due to noise. If an A/D conversion operation has been stopped and then started, the voltage applied to the AV and AV pins becomes unstable, causing the accuracy of the A/D conversion to drop.
Page 264 CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES) (15) Internal equivalent circuit of ANI0 to ANI7 pins and permissible signal source impedance To complete sampling within the sampling time with sufficient A/D conversion accuracy, the impedance of the signal source such as a sensor must be sufficiently low.
Page 265: Chapter 14 Serial Interface Sio3
CHAPTER 14 SERIAL INTERFACE SIO3 14.1 Functions of Serial Interface SIO3 Serial interface SIO3 has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. For details, see 14.4.1 Operation stop mode. (2) 3-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCK3), serial output line (SO3), and serial input line (SI3).
Page 266: Configuration Of Serial Interface Sio3
CHAPTER 14 SERIAL INTERFACE SIO3 14.2 Configuration of Serial Interface SIO3 Serial interface SIO3 consists of the following hardware. Table 14-1. Configuration of Serial Interface SIO3 Item Configuration Register Serial I/O shift register 3 (SIO3) Control register Serial operation mode register 3 (CSIM3) (1) Serial I/O shift register 3 (SIO3) This is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock.
Page 267: Register To Control Serial Interface Sio3
CHAPTER 14 SERIAL INTERFACE SIO3 14.3 Register to Control Serial Interface SIO3 The serial interface SIO3 is controlled by serial operation mode register 3 (CSIM3). (1) Serial operation mode register 3 (CSIM3) This register is used to enable or disable SIO3’s serial clock, operation modes, and specific operations. CSIM3 is set by a 1-bit or 8-bit memory manipulation instruction.
Page 268 CHAPTER 14 SERIAL INTERFACE SIO3 Figure 14-2. Format of Serial Operation Mode Register 3 (CSIM3) Address: FFAFH After reset: 00H Symbol CSIM3 CSIE3 MODE SCL31 SCL30 CSIE3 Enable/disable specification for SIO3 Shift register operation Serial counter Port Note 1 Operation stop Clear Port function Note 2...
Page 269: Operations Of Serial Interface Sio3
CHAPTER 14 SERIAL INTERFACE SIO3 14.4 Operations of Serial Interface SIO3 This section explains the two modes of serial interface SIO3. 14.4.1 Operation stop mode Because serial transfer is not performed in this mode, the power consumption can be reduced. In addition, pins can be used as normal I/O ports.
Page 270: 3-Wire Serial I/O Mode
CHAPTER 14 SERIAL INTERFACE SIO3 14.4.2 3-wire serial I/O mode The 3-wire serial I/O mode can be used for connection to a peripheral IC incorporating a clocked serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCK3), serial output line (SO3), and serial input line (SI3).
Page 271 CHAPTER 14 SERIAL INTERFACE SIO3 Address: FFAFH After reset: 00H Symbol CSIM3 CSIE3 MODE SCL31 SCL30 CSIE3 Enable/disable specification for SIO3 Shift register operation Serial counter Port Note 1 Operation stop Clear Port function Note 2 Operation enable Count operation enable Serial function + port function MODE Transfer operation modes and flags...
Page 272 CHAPTER 14 SERIAL INTERFACE SIO3 (2) Communication operations In the 3-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is transmitted or received in synchronization with the serial clock. Serial I/O shift register 3 (SIO3) is shifted in synchronization with the falling edge of the serial clock. Transmission data is held in the SO3 latch and is output from the SO3 pin.
Page 273: Chapter 15 Serial Interface Csi1
CHAPTER 15 SERIAL INTERFACE CSI1 15.1 Functions of Serial Interface CSI1 Serial interface CSI1 has the following two modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not performed. In this mode, the power consumption can be reduced. (2) 3-wire serial I/O mode (MSB/LSB first selectable) This mode is used to transfer 8-bit data by using three lines: a serial clock line (SCK1) and two serial data lines (SI1 and SO1).
Page 274 CHAPTER 15 SERIAL INTERFACE CSI1 Figure 15-1. Block Diagram of Serial Interface CSI1 Internal bus Serial I/O shift Transmit buffer Output SI1/P23 SO1/P24 register 1 (SIO1) register 1 (SOTB1) selector Transmit data Output latch controller Transmit controller to f Clock start/stop controller Selector INTCSI1 &...
Page 275: Registers To Control Serial Interface Csi1
CHAPTER 15 SERIAL INTERFACE CSI1 15.3 Registers to Control Serial Interface CSI1 Serial interface CSI1 is controlled by the following two registers. • Serial operation mode register 1 (CSIM1) • Serial clock select register 1 (CSIC1) (1) Serial operation mode register 1 (CSIM1) This register is used to select an operation mode and enable or disable the operation.
Page 276 CHAPTER 15 SERIAL INTERFACE CSI1 (2) Serial clock select register 1 (CSIC1) This register is used to select the phase of the data clock and the transfer clock. This register is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 10H.
Page 277: Operations Of Serial Interface Csi1
CHAPTER 15 SERIAL INTERFACE CSI1 15.4 Operations of Serial Interface CSI1 Serial interface CSI1 can be used in the following two modes. • Operation stop mode • 3-wire serial I/O mode 15.4.1 Operation stop mode Serial transfer is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P23/SI1, P24/SO1, and P25/SCK1 pins can be used as normal I/O port pins in this mode.
Page 278 CHAPTER 15 SERIAL INTERFACE CSI1 (a) Serial operation mode register 1 (CSIM1) This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Note 1 Address: FFB0H After reset: 00H R/W Symbol CSIM1 CSIE1...
Page 279 CHAPTER 15 SERIAL INTERFACE CSI1 (b) Serial clock select register 1 (CSIC1) This register is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the value of this register to 10H. Address: FFB1H After reset: 10H R/W Symbol CSIC1 CKP1...
Page 280 CHAPTER 15 SERIAL INTERFACE CSI1 (2) Setting of port <1> Transmit/receive mode (a) To use externally input clock as system clock (SCK1) Bit 3 (PM23) of port mode register 2: Set to 1 Bit 4 (PM24) of port mode register 2: Cleared to 0 Bit 5 (PM25) of port mode register 2: Set to 1 Bit 4 (P24) of port 2: Cleared to 0 (b) To use internal clock as system clock (SCK1)
Page 281 CHAPTER 15 SERIAL INTERFACE CSI1 (3) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD1) of serial operation mode register 1 (CSIM1) is 1. Transmission/reception is started when a value is written to transmit buffer register 1 (SOTB1).
Page 282 CHAPTER 15 SERIAL INTERFACE CSI1 Figure 15-4. Timing in 3-Wire Serial I/O Mode (2/2) (2) Transmission/reception timing (Type 2; TRMD1 = 1, DIR1 = 0, CKP1 = 0, DAP1 = 1) SCK1 Read/write trigger SOTB1 55H (communication data) SIO1 CSOT1 INTCSI1 CSIIF1 SI1 (receives AAH)
Page 283 CHAPTER 15 SERIAL INTERFACE CSI1 Figure 15-5. Timing of Clock/Data Phase (a) Type 1; CKP1 = 0, DAP1 = 0 SCK1 SI1 capture Writing to SOTB1 or reading from SIO1 CSIIF1 CSOT1 (b) Type 2; CKP1 = 0, DAP1 = 1 SCK1 SI1 capture Writing to SOTB1 or...
Page 284 CHAPTER 15 SERIAL INTERFACE CSI1 (4) Timing of output to SO1 pin (first bit) When communication is started, the value of transmit buffer register 1 (SOTB1) is output from the SO1 pin. The output operation of the first bit at this time is explained below. Figure 15-6.
Page 285 CHAPTER 15 SERIAL INTERFACE CSI1 (5) Output value of SO1 pin (last bit) After communication has been completed, the SO1 pin holds the output value of the last bit. Figure 15-7. Output Value of SO1 Pin (Last Bit) (1) Type 1; CKP1 = 0 and DAP1 = 0 (or CKP1 = 1, DAP1 = 0) SCK1 Writing to SOTB1 or ( ←...
Page 286: Chapter 16 Serial Interface Uart0
CHAPTER 16 SERIAL INTERFACE UART0 16.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. For details, see 16.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode (fixed to LSB-first) This mode enables full-duplex operation wherein one byte of data after the start bit is transmitted and received.
Page 287 CHAPTER 16 SERIAL INTERFACE UART0 Figure 16-1. Block Diagram of Serial Interface UART0 Internal bus Asynchronous serial interface mode register 0 (ASIM0) Receive TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0 buffer register 0 (RXB0) Asynchronous serial interface status register 0 (ASIS0) Transmit Receive shift...
Page 288: Configuration Of Serial Interface Uart0
CHAPTER 16 SERIAL INTERFACE UART0 16.2 Configuration of Serial Interface UART0 Serial interface UART0 consists of the following hardware. Table 16-1. Configuration of Serial Interface (UART0) Item Configuration Registers Transmit shift register 0 (TXS0) Receive shift register 0 (RX0) Receive buffer register 0 (RXB0) Control registers Asynchronous serial interface mode register 0 (ASIM0) Asynchronous serial interface status register 0 (ASIS0)
Page 289: Registers To Control Serial Interface Uart0
CHAPTER 16 SERIAL INTERFACE UART0 (5) Receive controller The receive controller controls receive operations based on the values set to asynchronous serial interface mode register 0 (ASIM0). During a receive operation, it performs error checking, such as for parity errors, and sets various values to asynchronous serial interface status register 0 (ASIS0) according to the type of error that is detected.
Page 290 CHAPTER 16 SERIAL INTERFACE UART0 Figure 16-3. Format of Asynchronous Serial Interface Mode Register 0 (ASIM0) Address: FFA0H After reset: 00H Symbol ASIM0 TXE0 RXE0 PS01 PS00 ISRM0 TXE0 RXE0 Operation mode RxD0/P26 pin function TxD0/P27 pin function Operation stop Port function (P26) Port function (P27) UART mode...
Page 291 CHAPTER 16 SERIAL INTERFACE UART0 (2) Asynchronous serial interface status register 0 (ASIS0) When a receive error occurs in UART mode, this register indicates the type of error. ASIS0 can be read by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 16-4.
Page 292 CHAPTER 16 SERIAL INTERFACE UART0 Figure 16-5. Format of Baud Rate Generator Control Register 0 (BRGC0) Address: FFA2H After reset: 00H Symbol BRGC0 TPS02 TPS01 TPS00 MDL03 MDL02 MDL01 MDL00 TPS02 TPS01 TPS00 Source clock selection for 5-bit counter Setting prohibited —...
Page 293: Serial Interface Uart0 Operations
CHAPTER 16 SERIAL INTERFACE UART0 16.4 Serial Interface UART0 Operations This section explains the two modes of serial interface UART0. 16.4.1 Operation stop mode Because serial transfer is not performed during this mode, the power consumption can be reduced. In addition, pins can be used as normal ports. (1) Register settings Operation stop mode is set by asynchronous serial interface mode register 0 (ASIM0).
Page 294: Asynchronous Serial Interface (Uart) Mode
CHAPTER 16 SERIAL INTERFACE UART0 16.4.2 Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data after the start bit is transmitted or received. The on-chip baud rate generator dedicated to UART enables communications using a wide range of selectable baud rates.
Page 295 CHAPTER 16 SERIAL INTERFACE UART0 Address: FFA0H After reset: 00H Symbol ASIM0 TXE0 RXE0 PS01 PS00 ISRM0 TXE0 RXE0 Operation mode RxD0/P26 pin function TxD0/P27 pin function Operation stop Port function (P26) Port function (P27) UART mode Serial function (RxD0) (receive only) UART mode Port function (P26)
Page 296 CHAPTER 16 SERIAL INTERFACE UART0 (b) Asynchronous serial interface status register 0 (ASIS0) ASIS0 can be read by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Address: FFA1H After reset: 00H Symbol ASIS0 OVE0 Parity error flag No parity error...
Page 297 CHAPTER 16 SERIAL INTERFACE UART0 (c) Baud rate generator control register 0 (BRGC0) BRGC0 is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Address: FFA2H After reset: 00H Symbol BRGC0 TPS02 TPS01 TPS00 MDL03...
Page 298 CHAPTER 16 SERIAL INTERFACE UART0 The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. • Transmit/receive clock generation for baud rate by using main system clock The main system clock is divided to generate the transmit/receive clock. The baud rate generated from the main system clock is determined according to the following formula.
Page 299 CHAPTER 16 SERIAL INTERFACE UART0 Table 16-3. Relationship Between Main System Clock and Baud Rate = 10 MHz = 9.8304 MHz = 8.3886 MHz = 8 MHz Baud Rate (bps) BRGC0 ERR (%) BRGC0 ERR (%) BRGC0 ERR (%) BRGC0 ERR (%) –...
Page 300 CHAPTER 16 SERIAL INTERFACE UART0 • Error tolerance range for baud rate The tolerance range for the baud rate depends on the number of bits per frame and the counter’s division rate [1/(16 + k)]. Figure 16-6 shows an example of the baud rate error tolerance range. Figure 16-6.
Page 301 CHAPTER 16 SERIAL INTERFACE UART0 (2) Communication operations (a) Data format Figure 16-7 shows the format of the transmit/receive data. Figure 16-7. Format of Transmit/Receive Data in Asynchronous Serial Interface 1 data frame Start Parity Stop bit Character bits 1 data frame consists of the following bits. •...
Page 302 CHAPTER 16 SERIAL INTERFACE UART0 (b) Parity types and operations The parity bit is used to detect bit errors in communication data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected.
Page 303 CHAPTER 16 SERIAL INTERFACE UART0 (c) Transmission The transmit operation is enabled if bit 7 (TXE0) of asynchronous serial interface mode register 0 (ASIM0) is set to 1, the transmit operation is started when transmit data is written to transmit shift register 0 (TXS0). A start bit, parity bit, and stop bit(s) are automatically added to the data.
Page 304 CHAPTER 16 SERIAL INTERFACE UART0 (d) Reception Receive operations are executed via level detection. The receive operation is enabled when “1” is set to bit 6 (RXE0) of asynchronous serial interface mode register 0 (ASIM0), and input via the RxD0 pin is sampled. The serial clock specified by BRGC0 is used to sample the RxD0 pin.
Page 305 CHAPTER 16 SERIAL INTERFACE UART0 (e) Receive errors Three types of errors can occur during a receive operation: parity error, framing error, or overrun error. If, as the result of data reception, an error flag is set to asynchronous serial interface status register 0 (ASIS0), a receive error interrupt request (INTSER0) will occur.
Page 306: Chapter 17 Serial Interface Iic0 ( Μ Pd780344Y, 780354Y Subseries Only)
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) 17.1 Functions of Serial Interface IIC0 Serial interface IIC0 has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption. (2) I C bus mode (multimaster supported) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCL0) line and a...
Page 307 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-1 shows a block diagram of serial interface IIC0. Figure 17-1. Block Diagram of Serial Interface IIC0 Internal bus IIC status register 0 (IICS0) MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IIC control register 0 (IICC0) Slave address...
Page 308 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-2 shows a serial bus configuration example. Figure 17-2. Serial Bus Configuration Example Using I C Bus Master CPU1 Master CPU2 Serial data bus SDA0 SDA0 Slave CPU1 Slave CPU2 Serial clock SCL0...
Page 309: Serial Interface Iic0 Configuration
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) 17.2 Serial Interface IIC0 Configuration Serial interface IIC0 consists of the following hardware. Table 17-1. Configuration of Serial Interface IIC0 Item Configuration Registers IIC shift register 0 (IIC0) Slave address register 0 (SVA0) Control registers IIC control register 0 (IICC0) IIC status register 0 (IICS0)
Page 310: Registers To Control Serial Interface Iic0
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (6) Serial clock counter This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIIC0).
Page 311 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-3. Format of IIC Control Register 0 (IICC0) (1/3) Address: FFA4H After reset: 00H Symbol IICC0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 IICE0 C operation enable Stops operation.
Page 312 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-3. Format of IIC Control Register 0 (IICC0) (2/3) WTIM0 Control of wait and interrupt request generation Interrupt request is generated at the eighth clock’s falling edge. Master mode: After output of eight clocks, clock output is set to low level and wait is set. Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
Page 313 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-3. Format of IIC Control Register 0 (IICC0) (3/3) SPT0 Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until it goes to high level.
Page 314 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (2) IIC status register 0 (IICS0) This register indicates the status of I IICS0 is read by a 1-bit or 8-bit memory manipulation instruction. RESET input sets IICS0 to 00H. Figure 17-4.
Page 315 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-4. Format of IIC Status Register 0 (IICS0) (2/3) COI0 Detection of matching addresses Addresses do not match. Addresses match. Condition for clearing (COI0 = 0) Condition for setting (COI0 = 1) •...
Page 316 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-4. Format of IIC Status Register 0 (IICS0) (3/3) STD0 Detection of start condition Start condition was not detected. Start condition was detected. This indicates that the address transfer period is in effect. Condition for clearing (STD0 = 0) Condition for setting (STD0 = 1) •...
Page 317 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (3) IIC transfer clock select register 0 (IICCL0) This register is used to set the transfer clock for the I C bus. IICCL0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets IICCL0 to 00H.
Page 318 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-5. Format of IIC Transfer Clock Select Register 0 (IICCL0) (2/2) CL00 Selection of transfer rate Standard mode High-speed mode CLX0 = 0 CLX0 = 1 Note 1 Note 3 Note 4 /88 (95.2 kHz)
Page 319: I C Bus Mode Functions
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) 17.4 I C Bus Mode Functions 17.4.1 Pin configuration The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows. (1) SCL0 ········· This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices.
Page 320: C Bus Definitions And Control Methods
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) 17.5 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the signals used by the I bus. Figure 17-8 shows the transfer timing for the “start condition”, “data”, and “stop condition” output via the I bus’s serial data bus.
Page 321: Addresses
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) 17.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines.
Page 322: Acknowledge (Ack) Signal
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) 17.5.4 Acknowledge (ACK) signal The acknowledge (ACK) signal is used by the transmitting and receiving devices to confirm serial data reception. The receiving device returns one ACK signal for each 8 bits of data it receives. The transmitting device normally receives an ACK signal after transmitting 8 bits of data.
Page 323: Stop Condition
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) 17.5.5 Stop condition When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed.
Page 324: Wait Signal (Wait)
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) 17.5.6 Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0 pin to low level notifies the communication partner of the wait status.
Page 325 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-14. Wait Signal (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKE0 = 1) Master and slave both wait Master after output of ninth clock IIC0 data write (cancel wait)
Page 326: I 2 C Interrupt Requests (Intiic0)
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) 17.5.7 I C interrupt requests (INTIIC0) The INTIIC0 interrupt request timing and IIC status register 0 (IICS0) settings corresponding to that timing are described below. (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) When WTIM0 = 0 SPT0 = 1...
Page 327 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 RW D7 to D0 AD6 to AD0 RW D7 to D0 1: IICS0 = 1000×110B...
Page 328 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 RW D7 to D0 D7 to D0 1: IICS0 = 1010×110B 2: IICS0 = 1010×000B 3: IICS0 = 1010×000B (Sets WTIM0)
Page 329 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (2) Slave device operation (when receiving slave address data (matches with SVA0)) (a) Start ~ Address ~ Data ~ Data ~ Stop When WTIM0 = 0 AD6 to AD0 RW D7 to D0 D7 to D0 1: IICS0 = 0001×110B...
Page 330 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop When WTIM0 = 0 (after restart, matches with SVA0) AD6 to AD0 RW D7 to D0 AD6 to AD0 RW D7 to D0 1: IICS0 = 0001×110B...
Page 331 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop When WTIM0 = 0 (after restart, extension code reception) AD6 to AD0 RW D7 to D0 AD6 to AD0 RW D7 to D0 1: IICS0 = 0001×110B...
Page 332 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop When WTIM0 = 0 (after restart, does not match with address (= not extension code)) AD6 to AD0 RW D7 to D0 AD6 to AD0 RW...
Page 333 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (3) Slave device operation (when receiving extension code) (a) Start ~ Code ~ Data ~ Data ~ Stop When WTIM0 = 0 AD6 to AD0 RW D7 to D0 D7 to D0 1: IICS0 = 0010×010B 2: IICS0 = 0010×000B...
Page 334 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop When WTIM0 = 0 (after restart, matches with SVA0) AD6 to AD0 RW D7 to D0 AD6 to AD0 RW D7 to D0 1: IICS0 = 0010×010B...
Page 335 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, extension code reception) AD6 to AD0 RW D7 to D0 AD6 to AD0 RW D7 to D0 1: IICS0 = 0010×010B...
Page 336 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match with address (= not extension code)) AD6 to AD0 RW D7 to D0 AD6 to AD0 RW...
Page 337 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (5) Arbitration loss operation (operation as slave after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data (i) When WTIM0 = 0 AD6 to AD0 RW D7 to D0 D7 to D0 1: IICS0 = 0101×110B (Example When ALD0 is read during interrupt servicing)
Page 338 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (b) When arbitration loss occurs during transmission of extension code (i) When WTIM0 = 0 AD6 to AD0 RW D7 to D0 D7 to D0 1: IICS0 = 0110×010B (Example When ALD0 is read during interrupt servicing) 2: IICS0 = 0010×000B 3: IICS0 = 0010×000B 4: IICS0 = 00000001B...
Page 339 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (6) Operation when arbitration loss occurs (no communication after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data (when WTIM0 = 1) AD6 to AD0 RW D7 to D0 D7 to D0 1: IICS0 = 01000110B (Example When ALD0 is read during interrupt servicing)
Page 340 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (c) When arbitration loss occurs during data transfer (i) When WTIM0 = 0 AD6 to AD0 RW D7 to D0 D7 to D0 1: IICS0 = 10001110B 2: IICS0 = 01000000B (Example When ALD0 is read during interrupt servicing) 3: IICS0 = 00000001B Remark : Always generated...
Page 341 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: unmatches with SVA0, WTIM0 = 1) AD6 to AD0 RW D7 to Dn AD6 to AD0 RW D7 to D0 1: IICS0 = 1000×110B...
Page 342 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (e) When loss occurs due to stop condition during data transfer AD6 to AD0 RW D7 to Dn 1: IICS0 = 1000×110B 2: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 ×...
Page 343 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 1 STT0 = 1 ↓ AD6 to AD0 RW D7 to D0 1: IICS0 = 1000×110B 2: IICS0 = 1000××00B (Sets STT0)
Page 344: Interrupt Request (Intiic0) Generation Timing And Wait Control
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) 17.5.8 Interrupt request (INTIIC0) generation timing and wait control The setting of bit 3 (WTIM0) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated and the corresponding wait control, as shown in Table 17-2.
Page 345: Address Match Detection Method
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) 17.5.9 Address match detection method When in I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. An address match can be detected automatically by hardware. An interrupt request (INTIIC0) occurs when a local address has been set to slave address register 0 (SVA0) and when the address set to SVA0 matches the slave address transmitted by the master device, or when an extension code has been received.
Page 346: Arbitration
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) 17.5.12 Arbitration When several master devices simultaneously output a start condition (when STT0 is set to 1 before STD0 is set Note to 1 ), communication among the master devices is performed as the number of clocks are adjusted until the data differs.
Page 347: Wakeup Function
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Table 17-4. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 During address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission During extension code transmission Read/write data after extension code transmission...
Page 348: Communication Reservation
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) 17.5.14 Communication reservation To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used.
Page 349 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-16. Communication Reservation Timing Write to Program processing STT0 = 1 IIC0 Communi- Set SPD0 Hardware processing cation and INTIIC0 STD0 reservation SCL0 SDA0 Output by master with bus access Remark IIC0: IIC shift register 0 STT0: Bit 1 of IIC control register 0 (IICC0)
Page 350: Other Cautions
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-18. Communication Reservation Protocol SET1 STT0 Sets STT0 flag (communication reservation) Define communication Defines that communication reservation is in effect reservation (defines and sets user flag to any part of RAM) Gets wait period set by software (see Table 17-5).
Page 351: Communication Operations
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) 17.5.16 Communication operations (1) Master operation An example of master operation is shown below. Figure 17-19. Master Operation Flowchart START IICCL0 ← ××H Select transfer clock IICC0 ← ××H IICE0 = SPIE0 = WTIM0 = 1 STT0 = 1 INTIIC0 = 1?
Page 352 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) (2) Slave operation An example of slave operation is shown below. Figure 17-20. Slave Operation Flowchart START IICC0 ← ××H IICE0 = 1 INTIIC0 = 1? EXC0 = 1? Communicate? COI0 = 1? LREL0 = 1...
Page 353: Timing Charts
CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) 17.6 Timing Charts When using the I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of IIC status register 0 (IICS0)) that specifies the data transfer direction and then starts serial communication with the slave device.
Page 354 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (1) Start condition ~ address Processing by master device IIC0 ← address IIC0 ←...
Page 355 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (2) Data Processing by master device IIC0 ← data IIC0 ← data IIC0 ACKD0 STD0...
Page 356 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (3) Stop condition Processing by master device IIC0 ← data IIC0 ←...
Page 357 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (1) Start condition ~ address Processing by master device IIC0 ← address IIC0 ←...
Page 358 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (2) Data Processing by master device IIC0 ← FFH Note IIC0 ←...
Page 359 CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY) Figure 17-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (3) Stop condition Processing by master device IIC0 ← FFH Note IIC0 ←...
Page 360: Chapter 18 Lcd Controller/Driver
CHAPTER 18 LCD CONTROLLER/DRIVER 18.1 LCD Controller/Driver Functions The internal LCD controller/driver of the µ PD780344, 780354, 780344Y, and 780354Y Subseries has the following functions. (1) Automatic output of segment signals and common signals by automatically reading display data memory (2) Internal booster circuit employed for LCD driver reference voltage generator (×3 only).
Page 361: Lcd Controller/Driver Configuration
CHAPTER 18 LCD CONTROLLER/DRIVER Table 18-2 shows the maximum number of pixels that can be displayed in each display mode. Table 18-2. Maximum Number of Pixels Displayed Bias Mode Time Division Common Signals Maximum Number of Pixels 12 (12 segments × 1 common) —...
Page 362 Internal bus Static/dynamic LCD display mode LCD gain adjust LCD clock control register 3 (LCDM3) register 0 (VLCG0) register 3 (LCDC3) display switching register 3 (SDSEL3) SEGREG0 SEGREG1 SEGREG2 SEGREG39 SEGREG3 LCDC LCDC LCDC LCDC SDSEL SDSEL SDSEL ..LCDON SCOC VLCON BLSEL...
Page 363: Registers To Control Lcd Controller/Driver
CHAPTER 18 LCD CONTROLLER/DRIVER 18.3 Registers to Control LCD Controller/Driver The LCD controller/driver can be controlled by using the following five types of registers. • LCD display mode register 3 (LCDM3) • LCD clock control register 3 (LCDC3) • LCD gain adjust register 0 (VLCG0) •...
Page 364 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-2. Format of LCD Display Mode Register 3 (LCDM3) Address: FF90H After reset: 00H Symbol LCDM3 LCDON SCOC VLCON BLSEL BLON LCDM0 LCDON Display control (enables output of display data) Display OFF (All segment output pins output unselect signals.) Display ON SCOC Output control of segment/common pins...
Page 365 CHAPTER 18 LCD CONTROLLER/DRIVER Cautions 1. Set the LCDON, SCOC, and VLCON bits in the following sequence: • To display LCD while LCD booster circuit is stopped (1) Set VLCON to 1. All the segment and common pins are in the GND output mode (SCOC = 0).
Page 366 CHAPTER 18 LCD CONTROLLER/DRIVER (2) LCD clock control register 3 (LCDC3) This register is used to select the LCD source clock and frame frequency. It is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H. Figure 18-4.
Page 367 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-5. Relationship Between Reference Clock Generating Frame Frequency, and Frame Frequency Static FLAME 3-time division FLAME 4-time division FLAME Remark f Reference clock that generates frame frequency LCD clock period : Frame period FLAME (3) LCD gain adjust register 0 (VLCG0) This register controls the voltage boost level during the voltage boost operation.
Page 368 CHAPTER 18 LCD CONTROLLER/DRIVER (4) Static/dynamic display switching register 3 (SDSEL3) This register is used to select the static or dynamic display mode of the segment pins (S0 to S11). It can be set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 00H.
Page 369 CHAPTER 18 LCD CONTROLLER/DRIVER (5) Pin function switching registers (PF8 to PF11) These registers are used to select whether the pins of ports 8 to 11 are used as port pins or segment pins in 1-bit units. These registers are set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the values of these registers to 00H.
Page 370: Lcd Display Ram
CHAPTER 18 LCD CONTROLLER/DRIVER 18.4 LCD Display RAM The LCD display data and the LCD blinking select bits corresponding to the LCD display data are mapped to addresses FA00H to FA27H. The lower 4 bits of each of these addresses are an LCD display data area, and the higher 4 bits are an LCD blinking select bit area.
Page 371: Lcd Controller/Driver Settings
CHAPTER 18 LCD CONTROLLER/DRIVER 18.5 LCD Controller/Driver Settings Set the LCD controller/driver as follows: Specify whether P80/S12 to P87/S19, P90/S20 to P97/S27, P100/S28 toP107/S35, and P110/S36 to P113/ S39 are used as segment output pins or port output pins, by using the pin function switching registers (PF8 to PF11).
Page 372: Common Signals And Segment Signals
CHAPTER 18 LCD CONTROLLER/DRIVER 18.6 Common Signals and Segment Signals An individual pixel on an LCD panel lights when the potential difference of the corresponding common signal and segment signal reaches or exceeds a given voltage (depending on the panel), and extinguishes when the potential difference drops lower than V (1) Common signals For common signals, the selection timing order is as shown in Table 18-5 according to the number of time divisions...
Page 373 CHAPTER 18 LCD CONTROLLER/DRIVER (3) Common signal and segment signal output waveforms The voltages shown in Figures 18-10 and 18-11 are output for the common signals and segment signals. The ±V ON voltage is only produced when the common signal and segment signal are both at the selection voltage;...
Page 374 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-11. Common Signal and Segment Signal Voltages and Phases (a) Static display mode Selected Not selected LCD0 Common signal LCD0 Segment signal Remark T: One LCDCL cycle (b) Dynamic display mode (1/3 bias method) Selected Not selected LCD0 LCD1...
Page 375: Supplying Lcd Drive Voltages
CHAPTER 18 LCD CONTROLLER/DRIVER 18.7 Supplying LCD Drive Voltages V , and V LCD0 LCD1 LCD2 The µ PD780344, 780354, 780344Y, 780354Y Subseries contains a booster circuit (×3 only) to generate a supply voltage to drive the LCD. The internal LCD reference voltage (V ) is output from the V pin.
Page 376: Display Modes
CHAPTER 18 LCD CONTROLLER/DRIVER 18.8 Display Modes 18.8.1 Static display example Figure 18-14 shows the connection of a static type 1-digit LCD panel with the display pattern shown in Figure 18- 13 with the segment (S0 to S11) and common (SCOM0) signals. The display example is “5,” and the display data memory contents (addresses FA00H to FA07H) correspond to this.
Page 377 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-14. Static LCD Panel Connection Example (SDSEL3n = 1: n = 0, 1) SCOM0 FA00H User’s Manual U15798EJ2V0UD...
Page 378 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-15. Static LCD Drive Waveform Examples LCD0 SCOM0 LCD0 LCD0 Display waveform SCOM0-S1 –V Non-display waveform SCOM0-S2 –V User’s Manual U15798EJ2V0UD...
Page 379: 3-Time-Division Display Example
CHAPTER 18 LCD CONTROLLER/DRIVER 18.8.2 3-time-division display example Figure 18-17 shows the connection of a 3-time-division type 13-digit LCD panel with the display pattern shown in Figure 18-16 with the segment signals (S0 to S38) and common signals (COM0 to COM2). The display example is “123456.7890123,”...
Page 380 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-17. 3-Time-Division LCD Panel Connection Example (SDSEL3n = 0: n = 0 to 2) COM3 Open COM2 COM1 COM0 FA00H FA10H FA20H FA27H Remarks 1. X’: Irrelevant bits because they have no corresponding segment in the LCD panel 2.
Page 381 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-18. 3-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) LCD0 LCD1 COM0 LCD2 LCD0 LCD1 COM1 LCD2 LCD0 LCD1 COM2 LCD2 LCD0 LCD1 LCD2 +1/3V COM0-S21 –1/3V –V +1/3V COM1-S21 –1/3V –V +1/3V COM2-S21 –1/3V –V User’s Manual U15798EJ2V0UD...
Page 382: 4-Time-Division Display Example
CHAPTER 18 LCD CONTROLLER/DRIVER 18.8.3 4-time-division display example Figure 18-20 shows the connection of a 4-time-division type 20-digit LCD panel with the display pattern shown in Figure 18-19 with the segment signals (S0 to S39) and common signals (COM0 to COM3). The display example is “123456.78901234567890,”...
Page 383 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-20. 4-Time-Division LCD Panel Connection Example (SDSEL3n = 0, n = 0 to 2) COM3 COM2 COM1 COM0 FA00H FA10H FA20H FA27H User’s Manual U15798EJ2V0UD...
Page 384 CHAPTER 18 LCD CONTROLLER/DRIVER Figure 18-21. 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) LCD0 LCD1 COM0 LCD2 LCD0 LCD1 COM1 LCD2 LCD0 LCD1 COM2 LCD2 LCD0 LCD1 COM3 LCD2 LCD0 LCD1 LCD2 +1/3V COM0-S28 –1/3V –V +1/3V COM1-S28 –1/3V –V Remark The waveforms of COM2-S28 and COM3-S28 are omitted.
Page 385: Simultaneous Driving Of Static Display And Dynamic Display
CHAPTER 18 LCD CONTROLLER/DRIVER 18.8.4 Simultaneous driving of static display and dynamic display Simultaneous driving of static display (S0 to S11) and dynamic display is possible with the µ PD780344, 780354, 780344Y, 780354Y Subseries. For register settings, refer to Figure 18-7. User’s Manual U15798EJ2V0UD...
Page 386: Chapter 19 Interrupt Functions
CHAPTER 19 INTERRUPT FUNCTIONS 19.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged even in an interrupt disabled state. It does not undergo priority control and is given top priority over all other interrupt requests. However, a non-maskable interrupt is held pending during servicing of another non-maskable interrupt.
Page 387 CHAPTER 19 INTERRUPT FUNCTIONS Table 19-1. Interrupt Source List Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Non- — INTWDT Watchdog timer overflow Internal 0004H maskable (with watchdog timer mode 1 selected) Maskable INTWDT Watchdog timer overflow...
Page 388 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal bus Interrupt Vector table Priority controller request address generator Standby release signal (B) Internal maskable interrupt Internal bus Vector table Priority controller Interrupt address generator request Standby release signal...
Page 389 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (INTKR) Internal bus Interrupt Vector table Falling Priority controller request edge address generator detector “1” when MEM = 01H Standby release signal (E) Software interrupt Internal bus Interrupt Vector table...
Page 390: Interrupt Function Control Registers
CHAPTER 19 INTERRUPT FUNCTIONS 19.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. • Interrupt request flag registers (IF0L, IF0H, IF1L) • Interrupt mask flag registers (MK0L, MK0H, MK1L) • Priority specification flag registers (PR0L, PR0H, PR1L) •...
Page 391 CHAPTER 19 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.
Page 392 CHAPTER 19 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, and MK1L are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are combined to form a 16-bit register MK0, they are set by a 16-bit memory manipulation instruction.
Page 393 CHAPTER 19 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are combined to form 16-bit register PR0, they are set by a 16-bit memory manipulation instruction.
Page 394 CHAPTER 19 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP6. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets the values of these registers to 00H.
Page 395 CHAPTER 19 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control nesting processing are mapped here.
Page 396: Interrupt Servicing Operations
CHAPTER 19 INTERRUPT FUNCTIONS 19.4 Interrupt Servicing Operations 19.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag and ISP flag are reset (0), and the contents of the vector table are loaded into PC and branched.
Page 397 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-7. Flowchart of Non-Maskable Interrupt Request Generation to Acknowledgment Start WDTM4 = 1 (with watchdog timer mode selected)? Interval timer Overflow in WDT? WDTM3 = 0 (with non-maskable interrupt selected)? Reset processing Interrupt request generation WDT interrupt servicing? Interrupt request held pending...
Page 398 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-9. Non-Maskable Interrupt Request Acknowledgment Operation (a) If a non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main routine Execution of NMI request <1> NMI request <1> NMI request <2> held pending NMI request <2>...
Page 399: Maskable Interrupt Request Acknowledge Operation
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if in the interrupt enable state (when IE flag is set to 1).
Page 400 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-10. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (Interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated with ××PR = 0?
Page 401: Software Interrupt Request Acknowledge Operation
CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-11. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC save, Interrupt servicing CPU processing jump to interrupt Instruction Instruction program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock) Figure 19-12.
Page 402: Nesting Processing
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.4 Nesting processing Nesting occurs when an interrupt request is acknowledged during execution of another interrupt. Nesting does not occur unless the interrupt request acknowledge enable state is selected (IE = 1) (except non- maskable interrupts). Also, when an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0).
Page 403 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-13. Nesting Examples (1/2) Example 1. Nesting occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI RETI...
Page 404 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-13. Nesting Examples (2/2) Example 3. Nesting does not occur because interrupt is not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx RETI (PR = 0) IE = 1 IE = 0 1 instruction execution RETI...
Page 405: Interrupt Request Hold
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.5 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 406: Chapter 20 Standby Function
CHAPTER 20 STANDBY FUNCTION 20.1 Standby Function and Configuration 20.1.1 Standby function The standby function is designed to reduce power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. The system clock oscillator continues oscillating.
Page 407: Standby Function Control Register
CHAPTER 20 STANDBY FUNCTION 20.1.2 Standby function control register The wait time after the STOP mode is released upon interrupt request is controlled with the oscillation stabilization time select register (OSTS). OSTS is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 04H.
Page 408: Standby Function Operations
CHAPTER 20 STANDBY FUNCTION 20.2 Standby Function Operations 20.2.1 HALT mode (1) HALT mode setting and operating statuses The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating statuses in the HALT mode are described below.
Page 409 CHAPTER 20 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released with the following three types of sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
Page 410 CHAPTER 20 STANDBY FUNCTION (c) Release by RESET input When the RESET signal is input, HALT mode is released. And, as in the case with normal reset operation, the program is executed after branch to the reset vector address. Figure 20-3. HALT Mode Release by RESET Input Wait HALT instruction : 13.1 ms)
Page 411 CHAPTER 20 STANDBY FUNCTION Table 20-3. HALT Mode Release Condition and Necessity of NOP Instruction Setting When Subclock Multiplied by 4 Is Used ( µ PD78F0354, 78F0354Y Only) Clock Status Release Condition NOP Instruction Setting (One Instruction) Subclock multiplied by 4 HALT mode during main RESET input Unnecessary...
Page 412: Stop Mode
CHAPTER 20 STANDBY FUNCTION 20.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V via a pull-up resistor to minimize the leakage current at the crystal oscillator.
Page 413 CHAPTER 20 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released by the following two types of sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. If interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out.
Page 414 CHAPTER 20 STANDBY FUNCTION (b) Release by RESET input The STOP mode is released when RESET signal is input, and after the lapse of the oscillation stabilization time, the reset operation is carried out. Figure 20-5. STOP Mode Release by RESET Input Wait STOP instruction : 13.1 ms)
Page 415: Chapter 21 Reset Function
CHAPTER 21 RESET FUNCTION 21.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
Page 416 CHAPTER 21 RESET FUNCTION Figure 21-2. Timing of Reset by RESET Input Oscillation Normal operation Reset period stabilization Normal operation (Reset processing) (Oscillation stop) time wait RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 21-3. Timing of Reset Due to Watchdog Timer Overflow Oscillation Normal operation Reset period...
Page 417 CHAPTER 21 RESET FUNCTION Table 21-1. Hardware Statuses After Reset (1/2) Hardware Status After Reset Note 1 Program counter (PC) Contents of reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2 General-purpose register...
Page 418 CHAPTER 21 RESET FUNCTION Table 21-1. Hardware Statuses After Reset (2/2) Hardware Status After Reset Watch timer Operation mode register 0 (WTNM0) Interrupt time select register (WTIM) Watchdog timer Clock select register (WDCS) Mode register (WDTM) Clock output controller Clock output select register (CKS) Note 1 A/D converter Conversion result register 0 (ADCR0)
Page 419: Chapter 22 Rom Correction
CHAPTER 22 ROM CORRECTION 22.1 ROM Correction Functions In the µ PD780344, 780354, 780344Y, 780354Y Subseries, part of a program in the mask ROM or flash memory can be released with a program in the internal expansion RAM. Instruction bugs found in the mask ROM or flash memory can be avoided, and program flow can be changed by using the ROM correction function.
Page 420 CHAPTER 22 ROM CORRECTION (1) Correction address registers 0 and 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the mask ROM or flash memory. ROM correction corrects two places (max.) of the program. Addresses are set to two registers, CORAD0 and CORAD1.
Page 421: Rom Correction Control Register
CHAPTER 22 ROM CORRECTION 22.3 ROM Correction Control Register ROM correction is controlled by the correction control register (CORCN). (1) Correction control register (CORCN) This register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1.
Page 422: Rom Correction Application
CHAPTER 22 ROM CORRECTION 22.4 ROM Correction Application (1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such as EEPROM ) outside the microcontroller. When two places should be corrected, store the branch destination judgment program as well. The branch destination judgment program checks which one of the addresses set to correction address register 0 and 1 (CORAD0 and CORAD1) generates the correction branch.
Page 423 CHAPTER 22 ROM CORRECTION (2) Assemble in advance the initialization routine as shown in Figure 22-5 to correct the program. Figure 22-5. Initialization Routine Initialization ROM correction Is ROM Note correction used? Load the contents of external nonvolatile memory into internal expansion RAM Correction address register setting ROM correction enabled Main program...
Page 424 CHAPTER 22 ROM CORRECTION Figure 22-6. ROM Correction Operation Internal ROM (on-chip flash memory) program start Does fetch address match with correction address? ROM correction Set correction status flag Correction branch (branch to address F7FDH) Correction program execution User’s Manual U15798EJ2V0UD...
Page 425: Rom Correction Example
CHAPTER 22 ROM CORRECTION 22.5 ROM Correction Example An example of ROM correction when the instruction at address 1000H “ADD A, #1” is changed to “ADD A, #2” is as follows. Figure 22-7. ROM Correction Example Internal ROM or Internal Expansion RAM on-chip flash memory F400H 0000H...
Page 426: Program Execution Flow
CHAPTER 22 ROM CORRECTION 22.6 Program Execution Flow Figures 22-8 and 22-9 show the program transition diagrams when ROM correction is used. Figure 22-8. Program Transition Diagram (When One Place Is Corrected) FFFFH F7FFH BR !JUMP F7FDH Internal expansion Correction program JUMP Internal ROM Correction place...
Page 427 CHAPTER 22 ROM CORRECTION Figure 22-9. Program Transition Diagram (When Two Places Are Corrected) FFFFH F7FFH BR !JUMP F7FDH Correction program 2 yyyyH Internal expansion Correction program 1 xxxxH Destination judge program JUMP Internal ROM (on-chip flash memory) Correction place 2 Internal ROM (on-chip flash memory) Correction place 1...
Page 428: Cautions On Rom Correction
CHAPTER 22 ROM CORRECTION 22.7 Cautions on ROM Correction (1) Address values set in correction address registers 0 and 1 (CORAD0 and CORAD1) must be addresses where instruction codes are stored. In addition, address values to be set must be the start address of the instruction code.
Page 429: Chapter 23 Μ Pd78F0354, 78F0354Y
CHAPTER 23 µ PD78F0354, 78F0354Y The µ PD78F0354 and 78F0354Y are provided as the flash memory versions of the µ PD780344, 780354, 780344Y, and 780354Y Subseries. The µ PD78F0354 and 78F0354Y incorporate flash memory on which a program can be written, erased and overwritten while mounted on the board.
Page 430 CHAPTER 23 µ PD78F0354, 78F0354Y Table 23-1. Differences Between µ PD78F0354 and 78F0354Y, and Mask ROM Versions Item Flash Memory Versions Mask ROM Versions µ PD78F0354 µ PD78F0354Y µ PD780343, µ PD780353, µ PD780343Y, µ PD780353Y, µ PD780344 µ PD780354 µ...
Page 431: Memory Size Switching Register
CHAPTER 23 µ PD78F0354, 78F0354Y 23.1 Memory Size Switching Register The µ PD78F0354 and 78F0354Y allow users to select the internal memory capacity using the memory size switching register (IMS) so that the same memory map as that of mask ROM versions with a different internal memory capacity can be achieved.
Page 432: Internal Expansion Ram Size Switching Register
CHAPTER 23 µ PD78F0354, 78F0354Y 23.2 Internal Expansion RAM Size Switching Register The internal expansion RAM size switching register (IXS) is used to set the internal expansion RAM capacity. IXS is set by an 8-bit memory manipulation instruction. RESET input sets the value of this register to 0CH. Caution Be sure to set IXS to 0BH as the initial setting of the program.
Page 433: Flash Memory Characteristics
CHAPTER 23 µ PD78F0354, 78F0354Y 23.3 Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL- PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the flash memory mounted on the target system (on-board).
Page 434: Communication Mode
CHAPTER 23 µ PD78F0354, 78F0354Y 23.3.2 Communication mode Use the communication mode shown in Table 23-3 to perform communication between the dedicated flash programmer and µ PD78F0354, 78F0354Y. Table 23-3. Communication Mode List Note 1 Communication Standard (TYPE) Setting Pins Used Number of V Mode Pulses...
Page 435 CHAPTER 23 µ PD78F0354, 78F0354Y Figure 23-5. Example of Connection with Dedicated Flash Programmer (1/2) (a) 3-wire serial I/O (SIO3) µ Dedicated flash programmer PD78F0354, 78F0354Y , AV /RESET RESET SCK3 SO/TxD SI/RxD Note , AV (b) 3-wire serial I/O (SIO3) with handshake µ...
Page 436 CHAPTER 23 µ PD78F0354, 78F0354Y Figure 23-5. Example of Connection with Dedicated Flash Programmer (2/2) (d) UART (UART0) µ Dedicated flash programmer PD78F0354, 78F0354Y , AV /RESET RESET SO/T SI/R Note , AV Note Connect this pin when the system clock is supplied from the dedicated flash programmer. If a resonator is already connected to the X1 pin, the CLK pin does not need to be connected.
Page 437: On-Board Pin Processing
CHAPTER 23 µ PD78F0354, 78F0354Y 23.3.3 On-board pin processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases.
Page 438 CHAPTER 23 µ PD78F0354, 78F0354Y (1) Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or set the other device to the output high impedance status.
Page 439 CHAPTER 23 µ PD78F0354, 78F0354Y <RESET pin> If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed.
Page 440: Connection Of Adapter For Flash Writing
CHAPTER 23 µ PD78F0354, 78F0354Y 23.3.4 Connection of adapter for flash writing The following figures show the examples of recommended connection when the adapter for flash writing is used. Figure 23-10. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O (SIO3) VDD (1.8 to 5.5 V) µ...
Page 441 CHAPTER 23 µ PD78F0354, 78F0354Y Figure 23-11. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O (SIO3) with Handshake VDD (1.8 to 5.5 V) µ PD78F0354 µ PD78F0354Y VPP2 (LVDD) SCK CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE User’s Manual U15798EJ2V0UD...
Page 442 CHAPTER 23 µ PD78F0354, 78F0354Y Figure 23-12. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O (CSI1) VDD (1.8 to 5.5 V) µ PD78F0354 µ PD78F0354Y VPP2 (LVDD) SCK CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE User’s Manual U15798EJ2V0UD...
Page 443 CHAPTER 23 µ PD78F0354, 78F0354Y Figure 23-13. Wiring Example for Flash Writing Adapter with UART (UART0) VDD (1.8 to 5.5 V) µ PD78F0354 µ PD78F0354Y VPP2 (LVDD) SCK CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE User’s Manual U15798EJ2V0UD...
Page 444: Chapter 24 Instruction Set
CHAPTER 24 INSTRUCTION SET This chapter lists each instruction set of the µ PD780344, 780354, 780344Y, 780354Y Subseries in table form. For details of each instruction’s operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). User’s Manual U15798EJ2V0UD...
Page 445: Conventions
CHAPTER 24 INSTRUCTION SET 24.1 Conventions 24.1.1 Operand identifiers and specification methods Operands are written in the “Operand” column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more methods, select one of them.
Page 446: Description Of "Operation" Column
CHAPTER 24 INSTRUCTION SET 24.1.2 Description of “operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 447: Operation List
CHAPTER 24 INSTRUCTION SET 24.2 Operation List Instruction Mnemonic Operands Bytes Operation Clocks Flag Group Z AC CY Note 1 Note 2 r ← byte 8-bit data r, #byte – transfer (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte –...
Page 448 CHAPTER 24 INSTRUCTION SET Instruction Mnemonic Operands Bytes Operation Clocks Flag Group Z AC CY Note 1 Note 2 rp ← word MOVW rp, #word – 16-bit data (saddrp) ← word saddrp, #word transfer sfrp ← word sfrp, #word – AX ←...
Page 449 CHAPTER 24 INSTRUCTION SET Instruction Mnemonic Operands Bytes Operation Clocks Flag Group Z AC CY Note 1 Note 2 A, CY ← A – byte × × × A, #byte – 8-bit operation (saddr), CY ← (saddr) – byte × ×...
Page 450 CHAPTER 24 INSTRUCTION SET Instruction Mnemonic Operands Bytes Operation Clocks Flag Group Z AC CY Note 1 Note 2 A ← A byte × 8-bit A, #byte – operation (saddr) ← (saddr) byte × saddr, #byte Note 3 A ← A r ×...
Page 451 CHAPTER 24 INSTRUCTION SET Instruction Mnemonic Operands Bytes Operation Clocks Flag Group Z AC CY Note 1 Note 2 AX, CY ← AX + word × × × 16-bit ADDW AX, #word – operation AX, CY ← AX – word ×...
Page 452 CHAPTER 24 INSTRUCTION SET Instruction Mnemonic Operands Bytes Operation Clocks Flag Group Z AC CY Note 1 Note 2 CY ← CY (saddr.bit) × AND1 CY, saddr.bit manipu- CY ← CY sfr.bit × CY, sfr.bit – late CY ← CY A.bit ×...
Page 453 CHAPTER 24 INSTRUCTION SET Instruction Mnemonic Operands Bytes Operation Clocks Flag Group Z AC CY Note 1 Note 2 (SP – 1) ← (PC + 3) , (SP – 2) ← (PC + 3) CALL !addr16 – Call/return PC ← addr16, SP ← SP – 2 (SP –...
Page 454 CHAPTER 24 INSTRUCTION SET Instruction Mnemonic Operands Bytes Operation Clocks Flag Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 saddr.bit, $addr16 Condi- tional PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 –...
Page 455: Instructions Listed By Addressing Type
CHAPTER 24 INSTRUCTION SET 24.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ User’s Manual U15798EJ2V0UD...
Page 456 CHAPTER 24 INSTRUCTION SET Note Second Operand #byte saddr !addr16 PSW [DE] [HL] [HL + byte] $addr16 None [HL + B] First Operand [HL + C] ADDC RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC SUBC SUBC SUBC SUBC SUBC ADDC SUBC B, C...
Page 457 CHAPTER 24 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note Second Operand #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW...
Page 458 CHAPTER 24 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP User’s Manual U15798EJ2V0UD...
Page 459: Chapter 25 Electrical Specifications
CHAPTER 25 ELECTRICAL SPECIFICATIONS Absolute maximum ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage µ PD78F0354, 78F0354Y only −0.5 to +10.5 Note 1 −0.3 to V Note 2 + 0.3 −0.3 to +0.3 , P20 to P27, P32 to P35, −0.3 to V Note 3 Note 2 Input voltage...
Page 460 CHAPTER 25 ELECTRICAL SPECIFICATIONS Note 1. Make sure that the following conditions of the V voltage application timing are satisfied when the flash memory is written. • When supply voltage rises 10 µ s or more after V must exceed V has reached the lower-limit value (1.8 V) of the operating voltage range (see a in the figure below).
Page 461 CHAPTER 25 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V Main system clock oscillator characteristics (T = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Ceramic Oscillation = 1.8 to 5.5 V Note 1 resonator frequency (f Oscillation After V reaches oscil-...
Page 462 CHAPTER 25 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V Subsystem clock oscillator characteristics (T = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Crystal Oscillation = 1.8 to 5.5 V 32.768 Note 1 resonator frequency (f Oscillation = 4.5 to 5.5 V Note 2...
Page 463 CHAPTER 25 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V DC characteristics (T = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit −1 Output current, Per pin high −20 All pins Output current, Per pin for P00 to P07, P20 to P27, P32 to P35, P40 to P43, P80 to P87, P90 to P97, P100 to P107, P110 to P113 Per pin for P30, P31, P70 to P73 Total for P80 to P87, P90 to P97, P100 to P107, P110 to...
Page 464 CHAPTER 25 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V DC characteristics (T = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.0 V ≤ V ≤ 5.5 V, Output voltage, P30, P31 = 15 mA 4.0 V ≤ V ≤...
Page 465 CHAPTER 25 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V = 1.8 to 5.5 V) ( µ PD78F0354, 78F0354Y) DC characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit = 5.0 V ±10% Note 2 Note 3 Power 10 MHz crystal When A/D converter stopped 15.0 30.0 supply...
Page 466 CHAPTER 25 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V DC characteristics (T = 1.8 to 5.5 V) (mask ROM version) Parameter Symbol Conditions MIN. TYP. MAX. Unit = 5.0 V ±10% Note 2 Note 3 Power 10 MHz crystal When A/D converter stopped 12.6 supply oscillation...
Page 467 CHAPTER 25 ELECTRICAL SPECIFICATIONS AC characteristics = −40 to +85°C, V (1) Basic operation (T = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.5 V ≤ V ≤ 5.5 V µ s Cycle time Operating with main system clock (minimum instruction 2.7 V ≤...
Page 468 CHAPTER 25 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V (2) Serial interface (T = 1.8 to 5.5 V) (a) SIO3 3-wire serial I/O mode (SCK3 ... internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.5 V ≤ V ≤...
Page 469 CHAPTER 25 ELECTRICAL SPECIFICATIONS (c) CSI1 3-wire serial I/O mode (SCK1 ... internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.5 V ≤ V ≤ 5.5 V SCK1 cycle time KCY3 2.7 V ≤ V < 4.5 V 1.8 V ≤...
Page 470 CHAPTER 25 ELECTRICAL SPECIFICATIONS (f) I C bus mode Parameter Symbol Standard Mode High-Speed Mode Unit MIN. MAX. MIN. MAX. SCL0 clock frequency − − µ s Bus free time (between stop and start condition) µ s Note 1 − −...
Page 471 CHAPTER 25 ELECTRICAL SPECIFICATIONS AC timing test points (excluding X1, XT1 input) 0.8V 0.8V Test points 0.2V 0.2V Clock timing (MIN.) X1 input (MAX.) (MIN.) XT1 input (MAX.) TI timing TIL0 TIH0 TM00, TI01 TILB TIHB TMIB0 TIL5 TIH5 TI50, TI51 User’s Manual U15798EJ2V0UD...
Page 472 CHAPTER 25 ELECTRICAL SPECIFICATIONS Interrupt request input timing INTL INTH INTP0 to INTP6 RESET input timing RESET User’s Manual U15798EJ2V0UD...
Page 473 CHAPTER 25 ELECTRICAL SPECIFICATIONS Serial transfer timing 3-wire serial I/O mode (SIO3, CSI1) KCYn SCK1, SCK3 SIKn KSIn SI1, SI3 Input data KSOn SO1, SO3 Output data n = 1 to 4 C bus mode SCL0 HD:DAT SU:STA HIGH HD:STA SU:STO SU:DAT HD:STA...
Page 474 CHAPTER 25 ELECTRICAL SPECIFICATIONS 8-bit A/D converter characteristics ( µ PD780344, 780344Y Subseries only) = −40 to +85°C, AV = 2.2 to 5.5 V, AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 4.5 V ≤ AV ≤...
Page 475 CHAPTER 25 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V LCD controller/driver characteristics (T = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit C1 to C4 = 0.47 µ F LCD reference Gain = 1 0.84 1.165 LCD2 voltage Gain = 1.5 1.26...
Page 476 CHAPTER 25 ELECTRICAL SPECIFICATIONS = −40 to +85°C) Data memory STOP mode low power supply voltage data retention characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention power V DDDR supply voltage µ A Data retention = 2.7 V DDDR DDDR power supply current...
Page 477 CHAPTER 25 ELECTRICAL SPECIFICATIONS Flash memory programming characteristics: µ PD78F0354, 78F0354Y only = 1.8 to 5.5 V, V = 0 V, V = 9.7 to 10.3 V) (1) Basic characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.5 V ≤ V ≤...
Page 478 CHAPTER 25 ELECTRICAL SPECIFICATIONS Flash write mode setting timing DRPSR RFCF COUNT PSRON PSRRF RESET (input) User’s Manual U15798EJ2V0UD...
Page 479: Chapter 26 Characteristics Curves Of Lcd Controller/Driver
CHAPTER 26 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES) (1) Characteristics curves of voltage boost stabilization time The following shows the characteristics curves of the time from the start of voltage boost (VLCON = 1) and the changes in the LCD output voltage (when GAIN is set to 0 (using the 3 V display panel)). LCD output voltage/voltage boost time = 4.5 V = 5 V...
Page 480 CHAPTER 26 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES) (2) Temperature characteristics of LCD output voltage The following shows the temperature characteristics curves of LCD output voltage. LCD output voltage/temperature (when GAIN = 0) LCD2 LCD1 LCD0 −40 −30 −20 −10 Temperature [°C] LCD output voltage/temperature (when GAIN = 1)
Page 481: Chapter 27 Package Drawings
CHAPTER 27 PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 16.00±0.20 its true position (T.P.) at maximum material condition. 14.00±0.20 14.00±0.20 16.00±0.20 1.00 1.00 0.22 +0.05 −0.04 0.08...
Page 482 CHAPTER 27 PACKAGE DRAWINGS 113-PIN PLASTIC FBGA (10x10) INDEX MARK (UNIT:mm) ITEM DIMENSIONS y1 S 10.00±0.10 10.00±0.10 0.20 1.28±0.10 0.35±0.06 0.93 φ φ 0.80 0.50 +0.05 –0.10 0.08 0.10 0.20 1.00 1.00 P113F1-80-DA3 Remark The dimensions and materials of the ES version are the same as those of the mass-produced version. User’s Manual U15798EJ2V0UD...
Page 483: Chapter 28 Recommended Soldering Conditions
CHAPTER 28 RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website.
Page 484 CHAPTER 28 RECOMMENDED SOLDERING CONDITIONS Table 28-1. Surface Mounting Type Soldering Conditions (2/3) (2) µ PD780343F1-×××-DA3: 113-pin plastic FBGA (10 × 10) µ PD780344F1-×××-DA3: 113-pin plastic FBGA (10 × 10) µ PD780353F1-×××-DA3: 113-pin plastic FBGA (10 × 10) µ PD780354F1-×××-DA3: 113-pin plastic FBGA (10 × 10) µ...
Page 485 CHAPTER 28 RECOMMENDED SOLDERING CONDITIONS Table 28-1. Surface Mounting Type Soldering Conditions (3/3) (3) µ PD78F0354F1-DA3: 113-pin plastic FBGA (10 × 10) µ PD78F0354YF1-DA3: 113-pin plastic FBGA (10 × 10) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. IR35-107-2 (at 210°C or higher), Count: Two times or less, Exposure limit: Note...
Page 486: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µ PD780344, 780354, 780344Y, 780354Y Subseries. Figure A-1 shows the configuration example of the tools. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT compatibles can be used for PC98-NX series computers.
Page 487 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Configuration of Development Tools Software package • Software package Debugging software Language processing software • Assembler package • Integrated debugger • C compiler package • System simulator • Device file Note 1 • C library source file Control software •...
Page 488: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 This package contains various software tools for 78K/0 Series development. Software package The following tools are included. RA78K0, CC78K0, ID78K0-NS, SM78K0, and various device files Part Number: µ S××××SP78K0 Remark ×××× in the part number differs depending on the OS used. µ...
Page 489: Control Software
APPENDIX A DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and OS used. µ S××××RA78K0 µ S××××CC78K0 ×××× Host Machine Supply Medium AB13 PC-9800 series, Windows (Japanese version) 3.5-inch 2HD FD BB13 IBM PC/AT compatibles Windows (English version) AB17 Windows (Japanese version)
Page 490: Debugging Tools (Hardware)
APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) IE-78K0-NS The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using a 78K/0 Series product. It corresponds to an integrated debugger (ID78K0-NS). This emulator should be used in combination with a power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine.
Page 491: Debugging Tools (Software)
APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) SM78K0 This is a system simulator for the 78K/0 Series. The SM78K0 is Windows-based System simulator software. It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine.
Page 492: Embedded Software
APPENDIX A DEVELOPMENT TOOLS A.7 Embedded Software RX78K0 is a real-time OS conforming to the µ ITRON specifications. RX78K0 Real-time OS A tool (configurator) for generating the nucleus of RX78K0 and multiple information tables is supplied. Used in combination with an assembler package (RA78K0) and device file (DF780354) (both sold separately).
Page 493: Package Drawing For Conversion Adapter (Tgc-100Sdw)
APPENDIX A DEVELOPMENT TOOLS A.8 Package Drawing for Conversion Adapter (TGC-100SDW) Figure A-2. TGC-100SDW Package Drawing (for Reference Only) F E D I J K P Q R S ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES 21.55 0.848 14.45 0.569 0.5x24=12 0.020x0.945=0.472 1.85±0.25 0.073±0.010...
Page 494: Appendix B Notes On Target System Design
APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following shows the conditions when connecting the emulation probe to the conversion adapter. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. Among the products described in this appendix, NP-100GC and NP-H100GC-TQ are products of Naito Densei Machida Mfg.
Page 495 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. Connection Conditions of Target System (When NP-100GC Is Used) Emulation board IE-780354-NS-EM1 Emulation probe NP-100GC 23 mm Connection adapter 11 mm TGC-100SDW 25 mm 21.55 mm Pin 1 21.55 mm 40 mm 34 mm Target system Figure B-3.
Page 496: Appendix C Register Index
APPENDIX C REGISTER INDEX C.1 Register Name Index A/D conversion result register 0 (ADCR0) ......................245 A/D conversion result register 1 (ADCR1) ......................224 A/D converter mode register 0 (ADM0) ...................... 226, 246 Analog input channel specification register 0 (ADS0) ................229, 249 Asynchronous serial interface mode register 0 (ASIM0) ..................
Page 497 APPENDIX C REGISTER INDEX Internal expansion RAM size switching register (IXS) ..................432 Interrupt mask flag register 0H (MK0H) ......................392 Interrupt mask flag register 0L (MK0L) ....................... 392 Interrupt mask flag register 1L (MK1L) ....................... 392 Interrupt request flag register 0H (IF0H) ......................391 Interrupt request flag register 0L (IF0L) ......................
Page 498 APPENDIX C REGISTER INDEX Processor clock control register (PCC) ....................... 115 Pull-up resistor option register 0 (PU0) ....................... 108 Pull-up resistor option register 2 (PU2) ....................... 108 Pull-up resistor option register 3 (PU3) ....................... 108 Pull-up resistor option register 4 (PU4) ....................... 108 Receive buffer register 0 (RXB0) ........................
Page 499: Register Symbol Index
APPENDIX C REGISTER INDEX C.2 Register Symbol Index ADCR0: A/D conversion result register 0 ......................245 ADCR1: A/D conversion result register 1 ......................224 ADM0: A/D converter mode register 0 ....................226, 246 ADS0: Analog input channel specification register 0 ................229, 249 ASIM0: Asynchronous serial interface mode register 0 .................
Page 500 APPENDIX C REGISTER INDEX MEM: Memory expansion mode register ...................... 109 MK0H: Interrupt mask flag register 0H ......................392 MK0L: Interrupt mask flag register 0L ......................392 MK1L: Interrupt mask flag register 1L ......................392 OSTS: Oscillation stabilization time select register ................215, 407 Port 0 ..............................
Page 501 APPENDIX C REGISTER INDEX SIO1: Serial I/O shift register 1 ........................274 SIO3: Serial I/O shift register 3 ........................266 SOTB1: Transmit buffer register 1 ........................274 SSCK: Subclock select register ........................117 SVA0: Slave address register 0 ........................309 TCAB0: Carrier generator output control register B0 ..................
Page 502: Appendix D Revision History
APPENDIX D REVISION HISTORY The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. (1/4) Edition Major Revision from Previous Edition Applied to: 2nd edition Deletion of indication “under development”...
Page 503 APPENDIX D REVISION HISTORY (2/4) Edition Major Revision from Previous Edition Applied to: 2nd edition Correction of Figure 9-2 Format of Watch Timer Operation Mode Register CHAPTER 9 WATCH TIMER 0 (WTNM0) Correction of 12.2 (3) Sample & hold circuit and (4) Voltage comparator CHAPTER 12 8-BIT A/D CONVERTER ( µ...
Page 504 APPENDIX D REVISION HISTORY (3/4) Edition Major Revision from Previous Edition Applied to: 2nd edition Combination of 17.2 (1) IIC shift register 0 (IIC0), (2) Slave address CHAPTER 17 SERIAL register 0 (SVA0), and 17.3 (5) IIC shift register 0 (IIC0), (6) Slave address INTERFACE IIC0 ( µ...
Page 505 APPENDIX D REVISION HISTORY (4/4) Edition Major Revision from Previous Edition Applied to: 2nd edition Correction of Figure 19-1 Basic Configuration of Interrupt Function (E) CHAPTER 19 INTERRUPT Software interrupt FUNCTIONS Addition of Caution in Figure 19-5 Format of External Interrupt Rising Edge Enable Register (EGP), External Interrupt Falling Edge Enable Register (EGN) Addition of description and Remark in 19.4.1 Non-maskable interrupt...

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NEC mPD780344 Series User Manual

Chapter 1 Outline

Chapter 2 Pin Functions

Chapter 3 Cpu Architecture

Chapter 4 Port Functions

Chapter 5 Clock Generator

Chapter 6 16-Bit Timer/Event Counter 0

Chapter 7 8-Bit Timers A0, B0

Chapter 8 8-Bit Timer/Event Counters 50, 51

Chapter 9 Watch Timer

Chapter 10 Watchdog Timer

Chapter 11 Clock Output Controller

CHAPTER 12 8-BIT A/D CONVERTER ( Μ PD780344, 780344Y SUBSERIES)

CHAPTER 13 10-BIT A/D CONVERTER ( Μ PD780354, 780354Y SUBSERIES)

Chapter 14 Serial Interface Sio3

Chapter 15 Serial Interface Csi1

Chapter 16 Serial Interface Uart0

CHAPTER 17 SERIAL INTERFACE IIC0 ( Μ PD780344Y, 780354Y SUBSERIES ONLY)

Chapter 18 Lcd Controller/Driver

Chapter 19 Interrupt Functions

Chapter 20 Standby Function

Chapter 21 Reset Function

Chapter 22 Rom Correction

CHAPTER 23 Μ PD78F0354, 78F0354Y

Chapter 24 Instruction Set

Chapter 25 Electrical Specifications

Chapter 26 Characteristics Curves of Lcd Controller/Driver

Chapter 27 Package Drawings

Chapter 28 Recommended Soldering Conditions

Appendix A Development Tools

Appendix B Notes on Target System Design

Appendix C Register Index

Appendix D Revision History

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Summary of Contents for NEC mPD780344 Series