Figure 7-2. Format of 16-Bit Timer Mode Control Register 0, 1 (TMC0, TMC1) (1/2)
After reset: 00H
R/W
7
6
TMCn
0
0
(n = 0, 1)
TMCn3
TMCn2
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
CHAPTER 7
TIMER/COUNTER FUNCTION
Address: FFFFF208H, FFFFF218H
5
4
3
0
0
TMCn3
Selects Operation
TMCn1
Mode and Clear Mode
0
Operation stops (TMn is
cleared to 0).
1
0
Free-running mode
1
0
Clears and starts at
valid edge of TIn0.
1
0
Clears and starts on
coincidence between
TMn and CRn0.
1
2
1
0
TMCn2
TMCn1
OVFn
Selects TOn Output
Timing
Not affected.
Coincidence between
TMn and CRn0 or
coincidence between
TMn and CRn1
Coincidence between
TMn and CRn0,
coincidence between
TMn and CRn1, or valid
edge of TIn0
Coincidence between
TMn and CRn0 or
coincidence between
TMn and CRn1
Coincidence between
TMn and CRn0,
coincidence between
TMn and CRn1, or valid
edge of TIn0
Coincidence between
TMn and CRn0 or
coincidence between
TMn and CRn1
Coincidence between
TMn and CRn0,
coincidence between
TMn and CRn1, or valid
edge of TIn0
Generation of Interrupt
Does not generate.
Generates on
coincidence between
TMn and CRn0 and
coincidence between
TMn and CRn1.
151