Appendix Cindex - NEC V850/SA1 mPD703015 Preliminary User's Manual

[Figure]
16-bit Timer -------------------------------------------------- 145
16-bit timer mode control register 0, 1 ---------------- 150
16-bit timer output control register 0, 1 --------------- 154
16-bit timer register 0, 1 ---------------------------------- 147
3-wire Serial I/O--------------------------------------------- 209
3-wire serial I/O mode-------------------------------209, 214
8-bit compare register 2-5-------------------------------- 180
8-bit counter 2-5 -------------------------------------------- 180
8-bit Timer---------------------------------------------------- 178
8-bit timer mode control register 2-5 ------------------ 182
[A]
A/D conversion result register--------------------------- 303
A/D converter------------------------------------------------ 301
A/D converter mode register ---------------------------- 205
Acknowledge ------------------------------------------------ 236
ADCR---------------------------------------------------------- 303
ADCRH-------------------------------------------------------- 303
Address match detection method ---------------------- 261
Address Space------------------------------------------------ 59
ADM------------------------------------------------------------ 305
ADS ------------------------------------------------------------ 307
Analog input channel specification register --------- 307
Arbitration ---------------------------------------------------- 263
Asynchronous serial interface (UARTn) mode ----- 280
Asynchronous serial interface mode register 0, 1 - 282
Asynchronous serial interface status registers 0, 1-- 284
[B]
Baud rate generator control registers 0, 1 ----------- 285
Baud rate generator mode control registers 0, 1--- 285
BUS CONTROL FUNCTION----------------------------- 83
Bus control pins----------------------------------------------- 83
Bus control unit (BCU) -------------------------------------- 27
Bus cycle control register ---------------------------------- 89
Bus Hold Function ------------------------------------------- 90
Bus Priority----------------------------------------------------- 99
Bus Timing ----------------------------------------------------- 92
Bus width ------------------------------------------------------- 85
Byte access ---------------------------------------------------- 85
[C]
Capture/compare control register 0, 1 ---------------- 153
Capture/compare register n0---------------------------- 148
APPENDIX C INDEX
Capture/compare register n1 ----------------------------149
Cascade connection (16-bit timer) mode -------------192
CLOCK GENERATION FUNCTION------------------131
Clock generator (CG) --------------------------------------- 27
Clock Output Function -------------------------------------132
Clock selector------------------------------------------------220
Command register ------------------------------------------- 82
Communication command--------------------------------366
Communication reservation ------------------------------266
Communication System -----------------------------------360
Communication Systems ---------------------------------366
CPU ------------------------------------------------------------- 27
CPU address space ----------------------------------------- 59
CPU Register Set -------------------------------------------- 54
CR00 -----------------------------------------------------------148
CR10 -----------------------------------------------------------148
CR20-CR50 --------------------------------------------------180
CRC0-----------------------------------------------------------153
CRC1-----------------------------------------------------------153
CRn1 -----------------------------------------------------------149
CSI0-CSI2 ----------------------------------------------------209
CSIM0-CSIM2 -----------------------------------------------211
CSIS0-CSIS2 ------------------------------------------------211
[D]
Data wait control register ---------------------------------- 87
DBC0 to DBC2-----------------------------------------------318
DCHC0 to DCHC2 ------------------------------------------319
DIOA0 to DIOA2---------------------------------------------317
DMA FUNCTIONS -----------------------------------------317
DMA byte count registers 0 to 2 ------------------------318
DMA channel control registers 0 to 2 ------------------319
DMA on-chip RAM address registers 0 to 2 ---------318
DMA peripheral I/O address registers 0 to 2---------317
DRA0 to DRA2-----------------------------------------------318
[E]
EGN0-----------------------------------------------------------332
EGP0-----------------------------------------------------------332
Error detection -----------------------------------------------262
Exception Trap ----------------------------------------------124
Extension code ----------------------------------------------262
External event counter ----------------------------- 146, 168
external event counter-------------------------------------187
External expansion mode---------------------------------- 69
383