NEC mPD78F0730 Preliminary User's Manual

8-bit single-chip microcontroller

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Preliminary User's Manual

µPD78F0730

8-Bit Single-Chip Microcontroller

PD78F0730

Document No. U19014EJ1V0UD00 (1st edition)

Date Published December 2007 NS CP(K)

Printed in Japan

Downloaded from

Elcodis.com

electronic components distributor

2007

Table of Contents

Summary of Contents for NEC mPD78F0730

Page 1 Preliminary User’s Manual µPD78F0730 8-Bit Single-Chip Microcontroller µ PD78F0730 Document No. U19014EJ1V0UD00 (1st edition) Date Published December 2007 NS CP(K) 2007 Printed in Japan Downloaded from Elcodis.com electronic components distributor...
Page 2 [MEMO] Preliminary User’s Manual U19014EJ1V0UD Downloaded from Elcodis.com electronic components distributor...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the µ PD78F0730 and design and develop application systems and programs for this device. The target product is as follows. µ PD78F0730 Purpose This manual is intended to give users an understanding of the functions described in the Organization below.
Page 6 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: ××× (overscore over pin and signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information ...
Page 7 Document No. SEMICONDUCTOR SELECTION GUIDE − Products and Packages − X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual”...
Page 8: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE..........................14 Features ............................ 14 Applications..........................14 Ordering Information ....................... 15 Pin Configuration (Top View)....................15 Block Diagram .......................... 17 Outline of Functions ........................ 18 CHAPTER 2 PIN FUNCTIONS ....................... 20 Pin Function List ........................20 Description of Pin Functions ....................22 2.2.1 P00 and P01 (port 0) .........................
Page 9 Operand Address Addressing ....................51 3.4.1 Implied addressing ........................51 3.4.2 Register addressing ........................52 3.4.3 Direct addressing ........................53 3.4.4 Short direct addressing ......................54 3.4.5 Special function register (SFR) addressing................55 3.4.6 Register indirect addressing.......................56 3.4.7 Based addressing ........................57 3.4.8 Based indexed addressing......................58 3.4.9 Stack addressing ........................59 CHAPTER 4 PORT FUNCTIONS......................
Page 10 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 ................113 Functions of 16-Bit Timer/Event Counter 00 ............... 113 Configuration of 16-Bit Timer/Event Counter 00..............114 Registers Controlling 16-Bit Timer/Event Counter 00 ............118 Operation of 16-Bit Timer/Event Counter 00 ............... 125 6.4.1 Interval timer operation......................
Page 11 CHAPTER 10 SERIAL INTERFACE UART6 ..................223 10.1 Functions of Serial Interface UART6 ................... 223 10.2 Configuration of Serial Interface UART6 ................224 10.3 Registers Controlling Serial Interface UART6 ..............227 10.4 Operation of Serial Interface UART6..................234 10.4.1 Operation stop mode........................234 10.4.2 Asynchronous serial interface (UART) mode ................235 10.4.3...
Page 12 13.4.2 Software interrupt request acknowledgement ................. 404 13.4.3 Multiple interrupt servicing....................... 405 13.4.4 Interrupt request hold ......................408 CHAPTER 14 STANDBY FUNCTION ....................409 14.1 Standby Function and Configuration................... 409 14.1.1 Standby function........................409 14.1.2 Registers controlling standby function..................409 14.2 Standby Function Operation....................
Page 13 19.6.5 REGC pin..........................460 19.6.6 Other signal pins ........................460 19.6.7 Power supply ...........................461 19.7 Programming Method......................461 19.7.1 Controlling flash memory ......................461 19.7.2 Flash memory programming mode ..................462 19.7.3 Selecting communication mode ....................463 19.7.4 Communication commands......................464 19.8 Security Settings........................465 19.9 Flash Memory Programming by Self-Programming............
Page 14: Chapter 1 Outline
NEC Electronics is not liable for problems occurring when the on- chip debug function is used.
Page 15: Ordering Information
CHAPTER 1 OUTLINE 1.3 Ordering Information • Flash memory version Part Number Package µ PD78F0730MC-CAB-AX 30-pin plastic SSOP (7.62 mm) 1.4 Pin Configuration (Top View) • 30-pin plastic SSOP (7.62 mm) P30/INTP1 P10/SCK10 P01/TI010/TO00 P11/SI10 P00/TI000 P12/SO10 P120/INTP0 P13/TxD6 RESET P14/RxD6 FLMD0 P122/X2/EXCLK/OCD0B...
Page 16 CHAPTER 1 OUTLINE Pin Identification Power supply for port SCK10: Serial clock input/output Ground for port SI10: Serial data input EXCLK: External clock input SO10: Serial data output (main system clock) TI000, TI010: Timer input FLMD0: Flash programming mode TI50, TI51: Timer input INTP0 to INTP3: External interrupt input...
Page 17: Block Diagram
CHAPTER 1 OUTLINE 1.5 Block Diagram TO00/TI010/P01 Port 0 16-bit timer/event P00, P01 counter 00 TI000/P00 RxD6/P14 Port 1 P10 to P17 TOH1/P16 8-bit timer H1 Port 3 P30 to P33 Internal Port 6 P60, P61 low-speed oscillator Port 12 P120-P122 Watchdog timer Clock output...
Page 18: Outline Of Functions
CHAPTER 1 OUTLINE 1.6 Outline of Functions (1/2) µ Item PD78F0730 Internal Flash memory 16 KB memory (self-programming Note supported) Note 1 KB High-speed RAM Note 2 KB Expansion RAM Memory space 64 KB Main system High-speed system X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) clock clock 12 or 16 MHz: V...
Page 19 CHAPTER 1 OUTLINE (2/2) µ Item PD78F0730 On-chip debug function Provided Power supply voltage = 4.0 to 5.5 V Operating ambient temperature = -40 to +85°C Package 30-pin plastic SSOP (7.62 mm) Caution The operating voltage range may change after completion of device evaluation. An outline of the timer is shown below.
Page 20: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are two types of pin I/O buffer power supplies: EV and V . The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins Port pins other than P121 and P122...
Page 21 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions Function Name Function After Reset Alternate Function − − − FLMD0 Flash memory programming mode setting INTP0 Input External interrupt request input for which the valid edge (rising Input port P120 edge, falling edge, or both rising and falling edges) can be INTP1 specified INTP2...
Page 22: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 and P01 (port 0) P00 and P01 function as a 2-bit I/O port. These pins also function as timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P00 and P01 function as a 2-bit I/O port.
Page 23: P10 To P17 (Port 1)
CHAPTER 2 PIN FUNCTIONS 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for serial interface data I/O, clock I/O, and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an 8-bit I/O port.
Page 24: P30 To P33 (Port 3)
CHAPTER 2 PIN FUNCTIONS 2.2.3 P30 to P33 (port 3) P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P30 to P33 function as a 4-bit I/O port.
Page 25: P120 To P122 (Port 12)
CHAPTER 2 PIN FUNCTIONS 2.2.5 P120 to P122 (port 12) P120 to P122 function as a 3-bit I/O port. These pins also function as pins for external interrupt request input, connecting resonator for main system clock, and external clock input for main system clock. The following operation modes can be specified in 1-bit units.
Page 26: Regc
CHAPTER 2 PIN FUNCTIONS 2.2.7 REGC This is the pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this µ pin to V via a capacitor (0.47 to 1.0 F: recommended). REGC Caution Keep the wiring length as short as possible for the broken-line part in the above figure. 2.2.8 USBM This is the pin for inputting/outputting data (−) to USB ports.
Page 27: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. See Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2.
Page 28 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 3-C P-ch Data N-ch Schmitt-triggered input with hysteresis characteristics Type 5-AG Type 5-AH Pull-up Pull-up P-ch P-ch enable enable Data Data P-ch P-ch IN/OUT IN/OUT Output Output N-ch N-ch...
Page 29 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 37 Type 38 RESET Data P-ch Output N-ch disable Input enable RESET Input Data enable P-ch Output N-ch disable Input enable Preliminary User’s Manual U19014EJ1V0UD Downloaded from Elcodis.com electronic components distributor...
Page 30: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space µ PD78F0730 can access a 64 KB memory space. Figure 3-1 shows the memory map. Cautions 1. Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) are fixed (IMS = CFH, IXS = 0CH).
Page 31 CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map F F F F H Special function registers (SFR) 256 × 8 bits F F 0 0 H F E F F H General-purpose registers 32 × 8 bits F E E 0 H 3 F F F H F E D F H Program area...
Page 32 CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory Block Address Value Number 0000H to 03FFH 0400H to 07FFH 0800H to 0BFFH 0C00H to 0FFFH 1000H to 13FFH...
Page 33: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). µ PD78F0730 incorporates internal ROM (flash memory), as shown below. Table 3-3. Internal ROM Capacity Part Number Internal ROM Structure...
Page 34 CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area A 5-byte area of 0080H to 0084H and 1080H to 1084H can be used as an option byte area. Set the option byte at 0080H to 0084H when the boot swap is not used, and at 0080H to 0084H and 1080H to 1084H when the boot swap is used.
Page 35: Internal Data Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space µ PD78F0730 incorporates the following RAMs. (1) Internal high-speed RAM Table 3-5. Internal High-Speed RAM Capacity Part Number Internal High-Speed RAM µ 1,024 × 8 bits (FB00H to FEFFH) PD78F0730 The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit registers per bank.
Page 36: Data Memory Addressing
CHAPTER 3 CPU ARCHITECTURE 3.1.5 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the µ...
Page 37: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers µ PD78F0730 incorporates the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
Page 38 CHAPTER 3 CPU ARCHITECTURE (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored.
Page 39 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) FEE0H FEE0H FEDFH...
Page 40 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) RET instruction (when SP = FEDEH) FEE0H FEE0H FEDFH PC15 to PC8...
Page 41: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
Page 42: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
Page 43 CHAPTER 3 CPU ARCHITECTURE Table 3-7. Special Function Register List (1/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF00H Port register 0 √ √ − FF01H Port register 1 −...
Page 44 CHAPTER 3 CPU ARCHITECTURE Table 3-7. Special Function Register List (2/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF33H Pull-up resistor option register 3 − √ −...
Page 45 CHAPTER 3 CPU ARCHITECTURE Table 3-7. Special Function Register List (3/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits − √ − FF73H UF0 endpoint 1 interface mapping register UF0E1IM −...
Page 46 CHAPTER 3 CPU ARCHITECTURE Table 3-7. Special Function Register List (4/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FFBDH 16-bit timer output control register 00 TOC00 √...
Page 47: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by contents of the program counter (PC), and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 48: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
Page 49 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
Page 50: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] Preliminary User’s Manual U19014EJ1V0UD Downloaded from...
Page 51: Preliminary User's Manual U19014Ej1V0Ud
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed.
Page 52: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes of an operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
Page 53: Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. This addressing can be carried out for all of the memory spaces. [Operand format] Identifier Description addr16...
Page 54: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 55: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 56: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all of the memory spaces.
Page 57: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 58: Based Indexed Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 59: Stack Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed.
Page 60: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions There are two types of pin I/O buffer power supplies: EV and V . The relationship between these power supplies and the pins is shown below. Table 4-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins Port pins other than P121 and P122...
Page 61: Port Configuration
CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions Function Name Function After Reset Alternate Function Port 0. Input port TI000 2-bit I/O port. TI010/TO00 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.
Page 62: Port 0
CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is a 2-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 and P01 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
Page 63 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P01 PU01 P-ch Alternate function PORT Output latch P01/TI010/TO00 (P01) PM01 Alternate function Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal Preliminary User’s Manual U19014EJ1V0UD Downloaded from Elcodis.com...
Page 64: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
Page 65 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P11 and P14 PU11, PU14 P-ch Alternate function PORT Output latch P11/SI10, (P11, P14) P14/RxD6 PM11, PM14 Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U19014EJ1V0UD...
Page 66 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P12 and P16 PU12, PU16 P-ch PORT Output latch (P12, P16) P12/SO10 P16/TOH1 PM12, PM16 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U19014EJ1V0UD...
Page 67 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P13 PU13 P-ch PORT Output latch (P13) P13/TxD6 PM13 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U19014EJ1V0UD Downloaded from Elcodis.com electronic components distributor...
Page 68 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P15 PU15 P-ch PORT Output latch (P15) PM15 Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U19014EJ1V0UD Downloaded from Elcodis.com electronic components distributor...
Page 69 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P17 PU17 P-ch Alternate function PORT Output latch P17/TI50/TO50 (P17) PM17 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U19014EJ1V0UD Downloaded from Elcodis.com...
Page 70: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P33 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3).
Page 71 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P33 PU33 P-ch Alternate function PORT Output latch P33/TI51/TO51 (P33) PM33 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal Preliminary User’s Manual U19014EJ1V0UD Downloaded from Elcodis.com...
Page 72: Port 6
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 6 Port 6 is a 2-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). The output of the P60 and P61 pins is N-ch open-drain output (6 V withstanding voltage). Reset signal generation sets port 6 to input mode.
Page 73: Port 12
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 12 Port 12 is a 3-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
Page 74 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P120 PU12 PU120 P-ch Alternate function PORT Output latch P120/INTP0 (P120) PM12 PM120 P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 Read signal WR××: Write signal Preliminary User’s Manual U19014EJ1V0UD Downloaded from Elcodis.com...
Page 75 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P121 and P122 OSCCTL OSCSEL/ OSCSELS PORT Output latch P122/X2/EXCLK/OCD0B (P122) PM12 PM122 OSCCTL OSCSEL OSCCTL EXCLK, OSCSEL PORT Output latch (P121) P121/X1/OCD0A PM12 PM121 OSCCTL OSCSEL P12: Port register 12 PM12: Port mode register 12 OSCCTL: Clock operation mode select register...
Page 76: Registers Controlling Port Function
CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following three types of registers. • Port mode registers (PM0, PM1, PM3, PM6, PM12) • Port registers (P0, P1, P3, P6, P12) • Pull-up resistor option registers (PU0, PU1, PU3, PU12) (1) Port mode registers (PM0, PM1, PM3, PM6, and PM12) These registers specify input or output mode for the port in 1-bit units.
Page 77 CHAPTER 4 PORT FUNCTIONS (2) Port registers (P0, P1, P3, P6, P12) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output latch is read.
Page 78 CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PU0, PU1, PU3, and PU12) These registers specify whether the on-chip pull-up resistors of P00 and P01, P10 to P17, P30 to P33, or P120 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3, and PU12.
Page 79: Port Function Operations
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit.
Page 80: Settings Of Port Mode Register And Output Latch When Using Alternate Function
CHAPTER 4 PORT FUNCTIONS 4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 4-5. Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function Pin Name Alternate Function PM××...
Page 81: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This circuit oscillates a clock of f = 12 or 16 MHz by connecting a resonator to X1 and X2.
Page 82: Configuration Of Clock Generator
CHAPTER 5 CLOCK GENERATOR (3) USB clock • PLL This circuit multiplies the clock generated by the X1 oscillator (f ) or external main system clock (f ) by 8 EXCLK or 12. Multiplication ratio x8 or x12 can be selected using the PLLM bit of the PLL control register (PLLC), and operation of PLL is started or stopped by setting the PLLSTOP bit.
Page 83 Figure 5-1. Block Diagram of Clock Generator Internal bus Oscillation stabilization Clock operation mode Main clock Main clock mode Processor clock control Main OSC select register mode register time select register (OSTS) register (MCM) register (PCC) control register (OSCCTL) (MCM) (MOC) AMPH EXCLK OSCSEL...
Page 84: Registers Controlling Clock Generator
CHAPTER 5 CLOCK GENERATOR Remarks 1. f X1 clock oscillation frequency 2. f Internal high-speed oscillation clock frequency 3. f External main system clock frequency EXCLK 4. f High-speed system clock oscillation frequency 5. f Main system clock oscillation frequency 6.
Page 85 CHAPTER 5 CLOCK GENERATOR (1) Clock operation mode select register (OSCCTL) This register selects the operation modes of the high-speed system clock and the gain of the on-chip oscillator. OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.
Page 86 CHAPTER 5 CLOCK GENERATOR (2) Processor clock control register (PCC) This register is used to select the CPU clock and the division ratio. PCC is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PCC to 01H. Figure 5-3.
Page 87 CHAPTER 5 CLOCK GENERATOR (3) Internal oscillation mode register (RCM) This register sets the operation mode of internal oscillators. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Note 1 Reset signal generation sets this register to 80H Figure 5-4.
Page 88 CHAPTER 5 CLOCK GENERATOR (4) Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU operates with a clock other than the high-speed system clock.
Page 89 CHAPTER 5 CLOCK GENERATOR (5) Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.
Page 90 CHAPTER 5 CLOCK GENERATOR (6) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked.
Page 91 CHAPTER 5 CLOCK GENERATOR (7) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released.
Page 92 CHAPTER 5 CLOCK GENERATOR (8) PLL control register (PLLC) This register sets the operation mode of PLL. PLLC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Figure 5-9. Format of PLL Control Register (PLLC) Address: FFA6H After reset: 01H Symbol...
Page 93 CHAPTER 5 CLOCK GENERATOR (9) USB clock control register (UCKC) This register controls the clock supplied to the USB macro. UCKC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 5-10.
Page 94: System Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. Figure 5-11 shows an example of the external circuit of the X1 oscillator. Figure 5-11.
Page 95 CHAPTER 5 CLOCK GENERATOR Figure 5-12. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched Preliminary User’s Manual U19014EJ1V0UD Downloaded from Elcodis.com...
Page 96: Internal High-Speed Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4.2 Internal high-speed oscillator µ An internal high-speed oscillator is incorporated in the PD78F0730. Oscillation can be controlled by the internal oscillation mode register (RCM). After a reset release, the internal high-speed oscillator automatically starts oscillation (16 MHz (TYP.)). 5.4.3 Internal low-speed oscillator µ...
Page 97: Clock Generator Operation
CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 5-1). • Main system clock f • High-speed system clock f X1 clock f External main system clock f EXCLK...
Page 98 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned On When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE = 1) 2.7 V (TYP.) Power supply voltage (V Internal reset signal <1> <2>...
Page 99: Controlling Clock
CHAPTER 5 CLOCK GENERATOR 5.6 Controlling Clock 5.6.1 Controlling high-speed system clock The following two types of high-speed system clocks are available. • X1 clock: Crystal/ceramic resonator is connected across the X1 pin. • External main system clock: External clock is input to the EXCLK pin. When the high-speed system clock is not used, the X1/P121 and X2/EXCLK/P122 pins can be used as I/O port pins.
Page 100 CHAPTER 5 CLOCK GENERATOR <4> Waiting for the stabilization of the oscillation of X1 clock Check the OSTC register and wait for the necessary time. During the wait time, other software processing can be executed with the internal high-speed oscillation clock.
Page 101 CHAPTER 5 CLOCK GENERATOR <2> Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock. XSEL MCM0 Selection of Main System Clock and Clock Supplied to Peripheral Hardware...
Page 102: Example Of Controlling Internal High-Speed Oscillation Clock
CHAPTER 5 CLOCK GENERATOR (b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock. When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the CPU clock to the internal high-speed oscillation clock.
Page 103 CHAPTER 5 CLOCK GENERATOR (2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock and peripheral hardware clock <1> • Restarting oscillation of the internal high-speed oscillation clock Note (See 5.6.2 (1) Example of setting procedure when restarting internal high-speed oscillation clock).
Page 104: Example Of Controlling Internal Low-Speed Oscillation Clock
CHAPTER 5 CLOCK GENERATOR <3> Executing the STOP instruction When the STOP instruction is executed, the system is placed in the STOP mode and internal high- speed oscillation clock is stopped. (b) To stop internal high-speed oscillation clock by setting RSTOP to 1 <1>...
Page 105: Example Of Controlling Usb Clock
CHAPTER 5 CLOCK GENERATOR 5.6.4 Example of controlling USB clock The clock of the USB macro (f = 48 Mhz) uses multiplication of division clock of high-speed system clock ( f by PLL. ● Example of setting procedure when supplying the USB clock from the high-speed system clock (f = 12/16 MHz) <1>...
Page 106: Clocks Supplied To Cpu And Peripheral Hardware
CHAPTER 5 CLOCK GENERATOR 5.6.5 Clocks supplied to CPU and peripheral hardware The following table shows the relation among the clocks supplied to the CPU and peripheral hardware, and setting of registers. Table 5-3. Clocks Supplied to CPU and Peripheral Hardware, and Register Setting Supplied Clock XSEL MCM0...
Page 107: Cpu Clock Status Transition Diagram
CHAPTER 5 CLOCK GENERATOR 5.6.6 CPU clock status transition diagram Figure 5-14 shows the CPU clock status transition diagram of this product. Figure 5-14. CPU Clock Status Transition Diagram When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE = 1) Regulator: Woken up Power ON Internal low-speed oscillator: Woken up...
Page 108 CHAPTER 5 CLOCK GENERATOR Table 5-4 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-4. CPU Clock Transition and SFR Register Setting Examples (1/3) (1) CPU operating with internal high-speed oscillation clock (B) after reset release (A) Status Transition SFR Register Setting (A) →...
Page 109 CHAPTER 5 CLOCK GENERATOR Table 5-4. CPU Clock Transition and SFR Register Setting Examples (2/3) (3) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Note Note Setting Flag of SFR Register AMPH EXCLK OSCSEL...
Page 110: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock
CHAPTER 5 CLOCK GENERATOR Table 5-4. CPU Clock Transition and SFR Register Setting Examples (3/3) (5) HALT mode (D) set while CPU is operating with high-speed system clock (C) Status Transition Setting (C) → (D) Executing HALT instruction (6) STOP mode (E) set while CPU is operating with high-speed system clock (C) (Setting sequence) Status Transition Setting...
Page 111: Time Required For Switchover Of Cpu Clock And Main System Clock
CHAPTER 5 CLOCK GENERATOR 5.6.8 Time required for switchover of CPU clock and main system clock By setting bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC), the division ratio of the main system clock can be changed. The actual switchover operation is not performed immediately after rewriting to PCC;...
Page 112: Conditions Before Clock Oscillation Is Stopped
CHAPTER 5 CLOCK GENERATOR Table 5-8. Conditions Before the Clock Oscillation Is Stopped and Flag Settings Clock Conditions Before Clock Oscillation Is Stopped Flag Settings of SFR (External Clock Input Disabled) Register Internal high-speed MCS = 1 RSTOP = 1 oscillation clock (The CPU is operating on a clock other than the internal high-speed oscillation clock)
Page 113: Chapter 6 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.1 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. (1) Interval timer 16-bit timer/event counter 00 generates an interrupt request at the preset time interval. (2) Square-wave output 16-bit timer/event counter 00 can output a square wave with any selected frequency.
Page 114: Configuration Of 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.2 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 includes the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 00 Item Configuration Time/counter 16-bit timer counter 00 (TM00) Register 16-bit timer capture/compare registers 000, 010 (CR000, CR010) Timer input TI000, TI010 pins Timer output...
Page 115 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read during operation, then input of the count clock is temporarily stopped, and the count value at that point is read.
Page 116 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (i) When CR000 is used as a compare register The value set in CR000 is constantly compared with the TM00 count value, and an interrupt request signal (INTTM000) is generated if they match. The value is held until CR000 is rewritten. (ii) When CR000 is used as a capture register The count value of TM00 is captured to CR000 when a capture trigger is input.
Page 117 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Table 6-2. Capture Operation of CR000 and CR010 External Input Signal TI000 Pin Input TI010 Pin Input Capture Operation Capture operation of CRC001 = 1 Set values of ES001 and CRC001 bit = 0 Set values of ES101 and CR000 TI000 pin input...
Page 118: Registers Controlling 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.3 Registers Controlling 16-Bit Timer/Event Counter 00 Registers used to control 16-bit timer/event counter 00 are shown below. • 16-bit timer mode control register 00 (TMC00) • Capture/compare control register 00 (CRC00) • 16-bit timer output control register 00 (TOC00) •...
Page 119 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FFBAH After reset: 00H Symbol <0> TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 Operation enable of 16-bit timer/event counter 00 Disables TM00 operation. Stops supplying operating clock. Asynchronously resets the internal circuit.
Page 120 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Capture/compare control register 00 (CRC00) CRC00 is the register that controls the operation of CR000 and CR010. Changing the value of CRC00 is prohibited during operation (when TMC003 and TMC002 = other than 00). CRC00 can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 121 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-7. Example of CR010 Capture Operation (When Rising Edge Is Specified) Valid edge Count clock N − 3 N − 2 N − 1 TM00 N + 1 TI000 Rising edge detection CR010 INTTM010 (3) 16-bit timer output control register 00 (TOC00) TOC00 is an 8-bit register that controls the TO00 pin output.
Page 122 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-8. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H Symbol <6> <5> <3> <2> <0> TOC00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger via software −...
Page 123 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) PRM00 is the register that sets the TM00 count clock and TI000 and TI010 pin input valid edges. Rewriting PRM00 is prohibited during operation (when TMC003 and TMC002 = other than 00). PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 124 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 pin for timer output, set PM01 and the output latches of P01 6 to 0. When using the P00/TI000 and P01/TO00/TI010 pins for timer input, set PM00 and PM01 to 1. At this time, the output latches of P00 and P01 may be 0 or 1.
Page 125: Operation Of 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4 Operation of 16-Bit Timer/Event Counter 00 6.4.1 Interval timer operation If bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register (TMC00) are set to 11 (clear & start mode entered upon a match between TM00 and CR000), the count operation is started in synchronization with the count clock.
Page 126 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-13. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CR000 used as compare register...
Page 127 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-14. Example of Software Processing for Interval Timer Function TM00 register 0000H Operable bits (TMC003, TMC002) CR000 register INTTM000 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers is performed before PRM00 register, setting the TMC003 and TMC002 bits to 11.
Page 128: Square Wave Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.2 Square wave output operation When 16-bit timer/event counter 00 operates as an interval timer (see 6.4.1), a square wave can be output from the TO00 pin by setting the 16-bit timer output control register 00 (TOC00) to 03H. When TMC003 and TMC002 are set to 11 (count clear &...
Page 129 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-17. Example of Register Settings for Square Wave Output Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CR000 used as compare register...
Page 130 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-18. Example of Software Processing for Square Wave Output Function TM00 register 0000H Operable bits (TMC003, TMC002) CR000 register TO00 pin output INTTM000 signal TO00 output control bit (TOE00) <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers is performed before...
Page 131: External Event Counter Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 External event counter operation When bits 1 and 0 (PRM001 and PRM000) of the prescaler mode register 00 (PRM00) are set to 11 (for counting up with the valid edge of the TI000 pin) and bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between TM00 and CR000 (INTTM000) is generated.
Page 132 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-20. Example of Register Settings in External Event Counter Mode (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CR000 used as compare register...
Page 133 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-21. Example of Software Processing in External Event Counter Mode TM00 register 0000H Operable bits (TMC003, TMC002) Compare register (CR000) Compare match signal (INTTM000) <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers is performed before PRM00 register, setting the TMC003 and TMC002 bits to 11.
Page 134: Operation In Clear & Start Mode Entered By Ti000 Pin Valid Edge Input
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 Operation in clear & start mode entered by TI000 pin valid edge input When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 10 (clear & start mode entered by the TI000 pin valid edge input) and the count clock (set by PRM00) is supplied to the timer/event counter, TM00 starts counting up.
Page 135 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-23. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Compare Register, CR010: Compare Register) (a) TOC00 = 13H, PRM00 = 10H, CRC00, = 00H, TMC00 = 08H TM00 register 0000H Operable bits...
Page 136 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: compare register, CR010: capture register) Figure 6-24. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Compare Register, CR010: Capture Register) Edge TI000 pin...
Page 137 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-25. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Compare Register, CR010: Capture Register) (2/2) (b) TOC00 = 13H, PRM00 = 10H, CRC00, = 04H, TMC00 = 0AH, CR000 = 0003H TM00 register 0003H 0000H...
Page 138 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Operation in clear & start mode by entered TI000 pin valid edge input (CR000: capture register, CR010: compare register) Figure 6-26. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Compare Register) Edge TI000 pin...
Page 139 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-27. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Compare Register) (1/2) (a) TOC00 = 13H, PRM00 = 10H, CRC00, = 03H, TMC00 = 08H, CR010 = 0001H TM00 register 0000H Operable bits...
Page 140 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-27. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Compare Register) (2/2) (b) TOC00 = 13H, PRM00 = 10H, CRC00, = 03H, TMC00 = 0AH, CR010 = 0003H TM00 register 0003H 0000H...
Page 141 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: capture register, CR010: capture register) Figure 6-28. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Capture Register) Operable bits TMC003, TMC002...
Page 142 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-29. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Capture Register) (2/3) (b) TOC00 = 13H, PRM00 = C0H, CRC00 = 05H, TMC00 = 0AH FFFFH TM00 register 0000H...
Page 143 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-29. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Capture Register) (3/3) (c) TOC00 = 13H, PRM00 = 00H, CRC00 = 07H, TMC00 = 0AH TM00 register 0000H Operable bits...
Page 144 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 0: Inverts TO00 output on match between CR000 and CR010.
Page 145 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (2/2) (d) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM001 PRM000 Count clock selection (setting TI000 valid edge is prohibited) 00: Falling edge detection 01: Rising edge detection...
Page 146 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-31. Example of Software Processing in Clear & Start Mode Entered by TI000 Pin Valid Edge Input TM00 register 0000H Operable bits (TMC003, TMC002) Count clear input (TI000 pin input) Compare register (CR000) Compare match interrupt (INTTM000) Compare register...
Page 147: Free-Running Timer Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 Free-running timer operation When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 01 (free- running timer mode), 16-bit timer/event counter 00 continues counting up in synchronization with the count clock. When it has counted up to FFFFH, the overflow flag (OVF00) is set to 1 at the next clock, and TM00 is cleared (to 0000H) and continues counting.
Page 148 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-33. Timing Example of Free-Running Timer Mode (CR000: Compare Register, CR010: Compare Register) • TOC00 = 13H, PRM00 = 00H, CRC00 = 00H, TMC00 = 04H FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Compare register (CR000) Compare match interrupt...
Page 149 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-35. Timing Example of Free-Running Timer Mode (CR000: Compare Register, CR010: Capture Register) • TOC00 = 13H, PRM00 = 10H, CRC00 = 04H, TMC00 = 04H FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Capture trigger input (TI000) Compare register...
Page 150 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Free-running timer mode operation (CR000: capture register, CR010: capture register) Figure 6-36. Block Diagram of Free-Running Timer Mode (CR000: Capture Register, CR010: Capture Register) Operable bits TMC003, TMC002 Timer counter Count clock (TM00) Capture register Interrupt signal (CR010)
Page 151 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-37. Timing Example of Free-Running Timer Mode (CR000: Capture Register, CR010: Capture Register) (1/2) (a) TOC00 = 13H, PRM00 = 50H, CRC00 = 05H, TMC00 = 04H FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Capture trigger input (TI000)
Page 152 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-37. Timing Example of Free-Running Timer Mode (CR000: Capture Register, CR010: Capture Register) (2/2) (b) TOC00 = 13H, PRM00 = C0H, CRC00 = 05H, TMC00 = 04H FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Capture trigger input (TI010)
Page 153 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-38. Example of Register Settings in Free-Running Timer Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 0: Inverts TO00 pin output on match between CR000 and CR010. 1: Inverts TO00 pin output on match between CR000 and CR010 and valid edge of TI000 pin.
Page 154 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-38. Example of Register Settings in Free-Running Timer Mode (2/2) (d) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM001 PRM000 Count clock selection (setting TI000 valid edge is prohibited) 00: Falling edge detection 01: Rising edge detection 10: Setting prohibited 11: Both edges detection...
Page 155 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-39. Example of Software Processing in Free-Running Timer Mode FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Compare register (CR000) Compare match interrupt (INTTM000) Compare register (CR010) Compare match interrupt (INTTM010) Timer output control bits (TOE00, TOC004, TOC001) TO00 pin output <1>...
Page 156: Ppg Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 PPG output operation A square wave having a pulse width set in advance by CR010 is output from the TO00 pin as a PPG (Programmable Pulse Generator) signal during a cycle set by CR000 when bits 3 and 2 (TMC003 and TMC002) of 16- bit timer mode control register 00 (TMC00) are set to 11 (clear &...
Page 157 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-41. Example of Register Settings for PPG Output Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CR000 used as compare register...
Page 158 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-42. Example of Software Processing for PPG Output Operation TM00 register 0000H Operable bits (TMC003, TMC002) Compare register (CR000) Compare match interrupt (INTTM000) Compare register (CR010) Compare match interrupt (INTTM010) Timer output control bits (TOE00, TOC004, TOC001) TO00 pin output N + 1...
Page 159: One-Shot Pulse Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.7 One-shot pulse output operation A one-shot pulse can be output by setting bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register 00 (TMC00) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI000 pin valid edge) and setting bit 5 (OSPE00) of 16-bit timer output control register 00 (TOC00) to 1.
Page 160 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-44. Example of Register Settings for One-Shot Pulse Output Operation (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 01: Free running timer mode 10: Clear and start mode by valid edge of TI000 pin.
Page 161 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-44. Example of Register Settings for One-Shot Pulse Output Operation (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) This register is used as a compare register when a one-shot pulse is output. When the value of TM00 matches that of CR000, an interrupt signal (INTTM000) is generated and the output level of the TO00 pin is inverted.
Page 162 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-45. Example of Software Processing for One-Shot Pulse Output Operation (1/2) FFFFH TM00 register 0000H Operable bits 01 or 10 (TMC003, TMC002) One-shot pulse enable bit (OSPE00) One-shot pulse trigger bit (OSPT00) One-shot pulse trigger input (TI000 pin) Overflow plug (OVF00)
Page 163 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-45. Example of Software Processing for One-Shot Pulse Output Operation (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers is performed PRM00 register, before setting the TMC003 and TMC002 bits. CRC00 register, Note TOC00 register...
Page 164: Pulse Width Measurement Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.8 Pulse width measurement operation TM00 can be used to measure the pulse width of the signal input to the TI000 and TI010 pins. Measurement can be accomplished by operating the 16-bit timer/event counter 00 in the free-running timer mode or by restarting the timer in synchronization with the signal input to the TI000 pin.
Page 165 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) Measuring the pulse width by using two input signals of the TI000 and TI010 pins (free-running timer mode) Set the free-running timer mode (TMC003 and TMC002 = 01). When the valid edge of the TI000 pin is detected, the count value of TM00 is captured to CR010.
Page 166 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Measuring the pulse width by using one input signal of the TI000 pin (free-running mode) Set the free-running timer mode (TMC003 and TMC002 = 01). The count value of TM00 is captured to CR000 in the phase reverse to the valid edge detected on the TI000 pin.
Page 167 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Measuring the pulse width by using one input signal of the TI000 pin (clear & start mode entered by the TI000 pin valid edge input) Set the clear & start mode entered by the TI000 pin valid edge (TMC003 and TMC002 = 10). The count value of TM00 is captured to CR000 in the phase reverse to the valid edge of the TI000 pin, and the count value of TM00 is captured to CR010 and TM00 is cleared (0000H) when the valid edge of the TI000 pin is detected.
Page 168 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-51. Example of Register Settings for Pulse Width Measurement (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 01: Free running timer mode 10: Clear and start mode entered by valid edge of TI000 pin.
Page 169 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-51. Example of Register Settings for Pulse Width Measurement (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) This register is used as a capture register. Either the TI000 or TI010 pin is selected as a capture trigger. When a specified edge of the capture trigger is detected, the count value of TM00 is stored in CR000.
Page 170 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-52. Example of Software Processing for Pulse Width Measurement (1/2) (a) Example of free-running timer mode FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Capture trigger input (TI000) Capture register 0000H (CR010) Capture interrupt (INTTM010) Capture trigger input (TI010)
Page 171 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-52. Example of Software Processing for Pulse Width Measurement (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers is performed PRM00 register, before setting the TMC003 and TMC002 bits. CRC00 register, port setting TMC003, TMC002 bits =...
Page 172: Special Use Of Tm00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.5 Special Use of TM00 6.5.1 Rewriting CR010 during TM00 operation µ In principle, rewriting CR000 and CR010 of the PD78F0730 when they are used as compare registers is prohibited while TM00 is operating (TMC003 and TMC002 = other than 00). However, the value of CR010 can be changed, even while TM00 is operating, using the following procedure if CR010 is used for PPG output and the duty factor is changed (change the value of CR010 immediately after its value matches the value of TM00.
Page 173 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Setting LVS00 and LVR00 Set LVS00 and LVR00 using the following procedure. Figure 6-53. Example of Flow for Setting LVS00 and LVR00 Bits Setting TOC00.OSPE00, TOC004, TOC001 bits <1> Setting of timer output operation Setting TOC00.TOE00 Setting...
Page 174: Cautions For 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.6 Cautions for 16-Bit Timer/Event Counter 00 (1) Restrictions for each channel of 16-bit timer/event counter 00 Table 6-3 shows the restrictions for each channel. Table 6-3. Restrictions for Each Channel of 16-Bit Timer/Event Counter 00 Operation Restriction −...
Page 175 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Timing of holding data by capture register (a) When the valid edge is input to the TI000/TI010 pin and the reverse phase of the TI000 pin is detected while CR000/CR010 is read, CR010 performs a capture operation but the read value of CR000/CR010 is not guaranteed.
Page 176 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (7) Operation of OVF00 flag (a) Setting OVF00 flag (1) The OVF00 flag is set to 1 in the following case, as well as when TM00 overflows. Select the clear & start mode entered upon a match between TM00 and CR000. ↓...
Page 177 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (9) Capture operation (a) When valid edge of TI000 is specified as count clock When the valid edge of TI000 is specified as the count clock, the capture register for which TI000 is specified as a trigger does not operate correctly.
Page 178: Chapter 7 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. • Interval timer • External event counter • Square-wave output • PWM output 7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware.
Page 179 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus 8-bit timer compare INTTM50 register 50 (CR50) Selector Match TI50/TO50/P17 Note 1 To UART6 8-bit timer TO50/TI50/P17 counter 50 (TM50) Clear Output latch Note 2 PM17...
Page 180 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) 8-bit timer counter 5n (TM5n) TM5n is an 8-bit register that counts the count pulses and is read-only. The counter is incremented in synchronization with the rising edge of the count clock. Figure 7-3.
Page 181: Registers Controlling 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. • Timer clock selection register 5n (TCL5n) • 8-bit timer mode control register 5n (TMC5n) •...
Page 182 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H Symbol TCL51 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 Count clock selection 12 MHz 16 MHz TI51 pin falling edge TI51 pin rising edge 12 MHz 16 MHz...
Page 183 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3>...
Page 184 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Note Address: FF43H After reset: 00H Symbol <7> <3> <2> <0> TMC51 TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 TCE51 TM51 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC516...
Page 185 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode registers 1 and 3 (PM1, PM3) These registers set port 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50 and P33/TO51/TI51 pins for timer output, clear PM17 and PM33 and the output latches of P17 and P33 to 0.
Page 186: Operations Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4 Operations of 8-Bit Timer/Event Counters 50 and 51 7.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.
Page 187 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-11. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H Count clock TM5n CR5n TCE5n INTTM5n Interval time (c) When CR5n = FFH Count clock TM5n FEH FFH 00H CR5n TCE5n INTTM5n Interrupt acknowledged...
Page 188: Operation As External Event Counter
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected.
Page 189: Square-Wave Output Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1.
Page 190: Pwm Output Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-13. Square-Wave Output Operation Timing Count clock N − 1 N − 1 TM5n count value Count start CR5n Note TO5n Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n).
Page 191 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) PWM output basic operation Setting <1> Set each register. • Clear the port output latch (P17 or P33) Note Note and port mode register (PM17 or PM33) to 0. • TCL5n: Select the count clock. •...
Page 192 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-14. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H CR5n TCE5n INTTM5n TO5n <2>...
Page 193 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 7-15. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH → Value is transferred to CR5n at overflow immediately after change. Count clock TM5n N N + 1 N + 2...
Page 194: Cautions For 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock.
Page 195: Chapter 8 8-Bit Timer H1
CHAPTER 8 8-BIT TIMER H1 8.1 Functions of 8-Bit Timer H1 8-bit timer H1 has the following functions. • Interval timer • Square-wave output • PWM output • Carrier generator 8.2 Configuration of 8-Bit Timer H1 8-bit timer H1 includes the following hardware. Table 8-1.
Page 196 Figure 8-1. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode 8-bit timer H carrier register 1 (TMHMD1) control register 1 (TMCYC1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 8-bit timer H 8-bit timer H RMC1 NRZB1 NRZ1 compare compare register 11...
Page 197 CHAPTER 8 8-BIT TIMER H1 (1) 8-bit timer H compare register 01 (CMP01) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in all of the timer operation modes. This register constantly compares the value set to CMP01 with the count value of 8-bit timer counter H1 and, when the two values match, generates an interrupt request signal (INTTMH1) and inverts the output level of TOH1.
Page 198: Registers Controlling 8-Bit Timer H1
CHAPTER 8 8-BIT TIMER H1 8.3 Registers Controlling 8-Bit Timer H1 The following four registers are used to control 8-bit timer H1. • 8-bit timer H mode register 1 (TMHMD1) • 8-bit timer H carrier control register 1 (TMCYC1) • Port mode register 1 (PM1) •...
Page 199 CHAPTER 8 8-BIT TIMER H1 Figure 8-4. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF6CH After reset: 00H <7> <1> <0> TMHMD1 TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) Count clock selection CKS12...
Page 200 CHAPTER 8 8-BIT TIMER H1 (2) 8-bit timer H carrier control register 1 (TMCYC1) This register controls the remote control output and carrier pulse output status of 8-bit timer H1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.
Page 201: Operation Of 8-Bit Timer H1
CHAPTER 8 8-BIT TIMER H1 8.4 Operation of 8-Bit Timer H1 8.4.1 Operation as interval timer/square-wave output When 8-bit timer counter H1 and compare register 01 (CMP01) match, an interrupt request signal (INTTMH1) is generated and 8-bit timer counter H1 is cleared to 00H. Compare register 11 (CMP11) is not used in interval timer mode.
Page 202 CHAPTER 8 8-BIT TIMER H1 Figure 8-8. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (Operation When 01H ≤ CMP01 ≤ FEH) Count clock Count start 01H 00H 8-bit timer counter H1 Clear Clear CMP01 TMHE1 INTTMH1 Interval time TOH1 <1>...
Page 203 CHAPTER 8 8-BIT TIMER H1 Figure 8-8. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP01 = FFH Count clock Count start 8-bit timer counter H1 Clear Clear CMP01 TMHE1 INTTMH1 TOH1 Interval time (c) Operation when CMP01 = 00H Count clock Count start 8-bit timer counter H1...
Page 204: Operation As Pwm Output
CHAPTER 8 8-BIT TIMER H1 8.4.2 Operation as PWM output In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register during timer operation is prohibited.
Page 205 CHAPTER 8 8-BIT TIMER H1 <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHE1 = 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is f , the PWM pulse output cycle and duty are as follows.
Page 206 CHAPTER 8 8-BIT TIMER H1 Figure 8-10. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 8-bit timer counter H1 00H 01H A5H 00H 01H 02H A5H 00H 01H 02H A5H 00H CMP01 CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <4>...
Page 207 CHAPTER 8 8-BIT TIMER H1 Figure 8-10. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP01 = FFH, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP01 CMP11 TMHE1...
Page 208 CHAPTER 8 8-BIT TIMER H1 Figure 8-10. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP01 = 01H, CMP11 = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter H1 CMP01 CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0)
Page 209 CHAPTER 8 8-BIT TIMER H1 Figure 8-10. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP11 (CMP11 = 02H → 03H, CMP01 = A5H) Count clock 8-bit timer 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H counter H1 CMP01...
Page 210: Carrier Generator Operation
CHAPTER 8 8-BIT TIMER H1 8.4.3 Carrier generator operation In the carrier generator mode, 8-bit timer H1 is used to generate the carrier signal of an infrared remote controller, and 8-bit timer/event counter 51 is used to generate an infrared remote control signal (time count). The carrier clock generated by 8-bit timer H1 is output in the cycle set by 8-bit timer/event counter 51.
Page 211 CHAPTER 8 8-BIT TIMER H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal.
Page 212 CHAPTER 8 8-BIT TIMER H1 Setting <1> Set each register. Figure 8-12. Register Setting in Carrier Generator Mode Setting 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHMD1 Timer output enabled Default setting of timer output level Carrier generator mode selection Count clock (f ) selection...
Page 213 CHAPTER 8 8-BIT TIMER H1 <10> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation, clear TMHE1 to 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is f , the carrier clock output cycle and duty are as follows.
Page 214 CHAPTER 8 8-BIT TIMER H1 Figure 8-13. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer H1 count clock 8-bit timer counter N 00H N 00H N 00H N 00H N 00H H1 count value CMP01 CMP11...
Page 215 CHAPTER 8 8-BIT TIMER H1 Figure 8-13. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer H1 count clock 8-bit timer counter N 00H 01H M 00H N 00H 01H M 00H H1 count value CMP01 CMP11...
Page 216 CHAPTER 8 8-BIT TIMER H1 Figure 8-13. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter 00H 01H 00H 01H H1 count value CMP01 <3> <3>’ CMP11 M (L) TMHE1 INTTMH1 <4>...
Page 217: Chapter 9 Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.1 Functions of Watchdog Timer The watchdog timer operates on the internal low-speed oscillation clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. Program loop is detected in the following cases.
Page 218: Configuration Of Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 9-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, and window open period are set by the option byte. Table 9-2.
Page 219: Register Controlling Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction.
Page 220: Operation Of Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.4 Operation of Watchdog Timer 9.4.1 Controlling operation of watchdog timer When the watchdog timer is used, its operation is specified by the option byte (0080H). • Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 18).
Page 221: Setting Overflow Time Of Watchdog Timer
CHAPTER 9 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LIOCP) of the option byte. LIOCP = 0 (Internal Low-Speed Oscillator LIOCP = 1 (Internal Low-Speed Oscillator Can Be Stopped by Software) Cannot Be Stopped)
Page 222: Setting Window Open Period Of Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.4.3 Setting window open period of watchdog timer µ In the PD78F0730, the window open period of the watchdog timer is 100%. Do not set any values other than 1, 1 (default) to bits 6 and 5 (WINDOW1, WINDOW0) of the option byte. Whenever WDTE is written to during the window open period (100%), as long as it is before the overflow time, the watchdog timer is cleared and starts counting again.
Page 223: Chapter 10 Serial Interface Uart6
CHAPTER 10 SERIAL INTERFACE UART6 10.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
Page 224: Configuration Of Serial Interface Uart6
CHAPTER 10 SERIAL INTERFACE UART6 10.2 Configuration of Serial Interface UART6 Serial interface UART6 includes the following hardware. Table 10-1. Configuration of Serial Interface UART6 Item Configuration Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6)
Page 225 Figure 10-1. Block Diagram of Serial Interface UART6 Filter INTSR6 Reception control INTSRE6 Receive shift register 6 (RXS6) Asynchronous serial Asynchronous serial Baud rate Receive buffer register 6 interface operation mode interface reception error generator (RXB6) register 6 (ASIM6) status register 6 (ASIS6) Reception unit Internal bus 8-bit timer/...
Page 226 CHAPTER 10 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6. If the data length is set to 7 bits, data is transferred as follows.
Page 227: Registers Controlling Serial Interface Uart6
CHAPTER 10 SERIAL INTERFACE UART6 10.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following seven registers. • Asynchronous serial interface operation mode register 6 (ASIM6) • Asynchronous serial interface reception error status register 6 (ASIS6) •...
Page 228 CHAPTER 10 SERIAL INTERFACE UART6 Figure 10-2. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) PS61 PS60 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
Page 229 CHAPTER 10 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0.
Page 230 CHAPTER 10 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
Page 231 CHAPTER 10 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = Figure 10-5.
Page 232 CHAPTER 10 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 233 CHAPTER 10 SERIAL INTERFACE UART6 (6) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P13/T D6 pin for serial interface data output, clear PM13 to 0 and set the output latch of P13 to 1. When using the P14/R D6 pin for serial interface data input, set PM14 to 1.
Page 234: Operation Of Serial Interface Uart6
CHAPTER 10 SERIAL INTERFACE UART6 10.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 10.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode.
Page 235: Asynchronous Serial Interface (Uart) Mode
CHAPTER 10 SERIAL INTERFACE UART6 10.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 236 CHAPTER 10 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 10-8 and 10-9 show the format and waveform example of the normal transmit/receive data. Figure 10-8. Format of Normal UART Transmit/Receive Data 1 data frame Start Parity...
Page 237 CHAPTER 10 SERIAL INTERFACE UART6 Figure 10-9. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity Stop 2. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start Parity...
Page 238 CHAPTER 10 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 239 CHAPTER 10 SERIAL INTERFACE UART6 (c) Normal transmission When bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6).
Page 240 CHAPTER 10 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized.
Page 241 CHAPTER 10 SERIAL INTERFACE UART6 Figure 10-11 shows an example of the continuous transmission processing flow. Figure 10-11. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Read ASIF6 TXBF6 = 0? Write TXB6. Transmission completion interrupt occurs?
Page 242 CHAPTER 10 SERIAL INTERFACE UART6 Figure 10-12 shows the timing of starting continuous transmission, and Figure 10-13 shows the timing of ending continuous transmission. Figure 10-12. Timing of Starting Continuous Transmission Start Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6...
Page 243 CHAPTER 10 SERIAL INTERFACE UART6 Figure 10-13. Timing of Ending Continuous Transmission Data (n − 1) Start Start Data (n) Parity Parity Stop Stop Stop INTST6 Data (n − 1) TXB6 Data (n) Data (n − 1) TXS6 Data (n) TXBF6 TXSF6 POWER6 or TXE6...
Page 244 CHAPTER 10 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the R D6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the R D6 pin input is detected.
Page 245 CHAPTER 10 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
Page 246 CHAPTER 10 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RXD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data.
Page 247: Dedicated Baud Rate Generator
CHAPTER 10 SERIAL INTERFACE UART6 10.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 248 CHAPTER 10 SERIAL INTERFACE UART6 Figure 10-17. Configuration of Baud Rate Generator POWER6 Baud rate generator POWER6, TXE6 (or RXE6) Selector 8-bit counter XCLK6 Match detector Baud rate 8-bit timer/ event counter 50 output CKSR6: TPS63 to TPS60 BRGC6: MDL67 to MDL60 Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6...
Page 249 CHAPTER 10 SERIAL INTERFACE UART6 (a) Baud rate The baud rate can be calculated by the following expression. XCLK6 • Baud rate = [bps] 2 × k : Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register XCLK6 Value set by MDL67 to MDL60 bits of BRGC6 register (k = 4, 5, 6, ..., 255) (b) Error of baud rate...
Page 250 CHAPTER 10 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 10-5. Set Data of Baud Rate Generator Baud Rate [bps] = 12.0 MHz = 16.0 MHz TPS63to TPS60 Calculated Value ERR[%] TPS63to TPS60 Calculated Value ERR[%] 300.487 0.16 300.481 0.16 600.962...
Page 251 CHAPTER 10 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 252 CHAPTER 10 SERIAL INTERFACE UART6 k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows.
Page 253: Cautions For Serial Interface Uart6
CHAPTER 10 SERIAL INTERFACE UART6 10.5 Cautions for Serial Interface UART6 (1) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected.
Page 254: Chapter 11 Serial Interface Csi10
CHAPTER 11 SERIAL INTERFACE CSI10 11.1 Functions of Serial Interface CSI10 Serial interface CSI10 has the following two modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption.
Page 255: Configuration Of Serial Interface Csi10
CHAPTER 11 SERIAL INTERFACE CSI10 11.2 Configuration of Serial Interface CSI10 Serial interface CSI10 includes the following hardware. Table 11-1. Configuration of Serial Interface CSI10 Item Configuration Controller Transmit controller Clock start/stop controller & clock phase controller Registers Transmit buffer register 10 (SOTB10) Serial I/O shift register 10 (SIO10) Control registers Serial operation mode register 10 (CSIM10)
Page 256 CHAPTER 11 SERIAL INTERFACE CSI10 (1) Transmit buffer register 10 (SOTB10) This register sets the transmit data. Transmission/reception is started by writing data to SOTB10 when bit 7 (CSIE10) and bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1. The data written to SOTB10 is converted from parallel data into serial data by serial I/O shift register 10, and output to the serial output pin (SO10).
Page 257: Registers Controlling Serial Interface Csi10
CHAPTER 11 SERIAL INTERFACE CSI10 11.3 Registers Controlling Serial Interface CSI10 Serial interface CSI10 is controlled by the following four registers. • Serial operation mode register 10 (CSIM10) • Serial clock selection register 10 (CSIC10) • Port mode register 1 (PM1) •...
Page 258 CHAPTER 11 SERIAL INTERFACE CSI10 (2) Serial clock selection register 10 (CSIC10) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 11-3.
Page 259 CHAPTER 11 SERIAL INTERFACE CSI10 (3) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using P10/SCK10 as the clock output pin of the serial interface, clear PM10 to 0, and set the output latches of P10 to 1.
Page 260: Operation Of Serial Interface Csi10
CHAPTER 11 SERIAL INTERFACE CSI10 11.4 Operation of Serial Interface CSI10 Serial interface CSI10 can be used in the following two modes. • Operation stop mode • 3-wire serial I/O mode 11.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P10/SCK10, P11/SI10, and P12/SO10 pins can be used as ordinary I/O port pins in this mode.
Page 261: 3-Wire Serial I/O Mode
CHAPTER 11 SERIAL INTERFACE CSI10 11.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK10), serial output (SO10), and serial input (SI10) lines.
Page 262 CHAPTER 11 SERIAL INTERFACE CSI10 The relationship between the register settings and pins is shown below. Table 11-2. Relationship Between Register Settings and Pins CSI10 CSIE10 TRMD10 PM11 PM12 PM10 Pin Function Operation SCK10/ SI10/P11 SO10/P12 × × × × ×...
Page 263 CHAPTER 11 SERIAL INTERFACE CSI10 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1. Transmission/reception is started when a value is written to transmit buffer register 10 (SOTB10).
Page 264 CHAPTER 11 SERIAL INTERFACE CSI10 Figure 11-5. Timing in 3-Wire Serial I/O Mode (2/2) (b) Transmission/reception timing (Type 2: TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 1) SCK10 Read/write trigger SOTB10 55H (communication data) SIO10 CSOT10 INTCSI10 CSIIF10 SI10 (input AAH)
Page 265 CHAPTER 11 SERIAL INTERFACE CSI10 Figure 11-6. Timing of Clock/Data Phase (a) Type 1: CKP10 = 0, DAP10 = 0, DIR10 = 0 SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 (b) Type 2: CKP10 = 0, DAP10 = 1, DIR10 = 0 SCK10 SI10 capture SO10...
Page 266 CHAPTER 11 SERIAL INTERFACE CSI10 (3) Timing of output to SO10 pin (first bit) When communication is started, the value of transmit buffer register 10 (SOTB10) is output from the SO10 pin. The output operation of the first bit at this time is described below. Figure 11-7.
Page 267 CHAPTER 11 SERIAL INTERFACE CSI10 Figure 11-7. Output Operation of First Bit (2/2) (c) Type 2: CKP10 = 0, DAP10 = 1 SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch First bit 2nd bit 3rd bit SO10 (d) Type 4: CKP10 = 1, DAP10 = 1 SCK10...
Page 268 CHAPTER 11 SERIAL INTERFACE CSI10 (4) Output value of SO10 pin (last bit) After communication has been completed, the SO10 pin holds the output value of the last bit. Figure 11-8. Output Value of SO10 Pin (Last Bit) (1/2) (a) Type 1: CKP10 = 0, DAP10 = 0 SCK10 ( ←...
Page 269 CHAPTER 11 SERIAL INTERFACE CSI10 Figure 11-8. Output Value of SO10 Pin (Last Bit) (2/2) (c) Type 2: CKP10 = 0, DAP10 = 1 SCK10 Writing to SOTB10 or ( ← Next request is issued.) reading from SIO10 SOTB10 SIO10 Output latch SO10 Last bit...
Page 270: Caution For Serial Interface Csi10
CHAPTER 11 SERIAL INTERFACE CSI10 (5) SO10 output (see (a) in Figure 11-1) The status of the SO10 output is as follows if bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) is cleared to 0. Table 11-3. SO10 Output Status Note 1 TRMD10 DAP10...
Page 271: Chapter 12 Usb Function Controller Usbf
CHAPTER 12 USB FUNCTION CONTROLLER USBF µ PD78F0730 has an internal USB function controller (USBF) conforming to the Universal Serial Bus Specification. 12.1 Overview • Conforms to the Universal Serial Bus Specification. • Supports 12 Mbps (full-speed) transfer • Endpoint for transfer incorporated Endpoint Name FIFO Size (Bytes) Transfer Type...
Page 272: Configuration
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) 12.2 Configuration USB function controller USBF includes the following hardware. Table 12-1. Configuration of USB Function Controller USBF (1/2) Item Configuration USB port pins USBP (+), USBM (–) Control registers UF0 EP0NAK register (UF0E0N) UF0 EP0NAKALL register (UF0E0NA) UF0 EPNAK register (UF0EN) UF0 EPNAK mask register (UF0ENM)
Page 273 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Table 12-1. Configuration of USB Function Controller USBF (2/2) Item Configuration Data hold registers UF0 EP0 read register (UF0E0R) UF0 EP0 length register (UF0E0L) UF0 EP0 setup register (UF0E0ST) UF0 EP0 write register (UF0E0W) UF0 bulk out 1 register (UF0BO1) UF0 bulk out 1 length register (UF0BO1L) UF0 bulk in 1 register (UF0BI1)
Page 274: Requests
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) 12.3 Requests 12.3.1 Automatic requests (1) Decode The following tables show the request formats and correspondence between requests and decoded values. Table 12-2. Request Format Offset Field Name bmRequestType bRequest wValue Lower side Higher side wIndex Lower side Higher side...
Page 275 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Table 12-3. Correspondence Between Requests and Decoded Values Offset Decoded Value Response Data Stage bmRequestType bRequest wValue wIndex wLength Request √ GET_INTERFACE STALL STALL √ GET_CONFIGURATION √ Note 1 GET_DESCRIPTOR Device √ Note 1 GET_DESCRIPTOR Configuration √...
Page 276 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Notes 3. The SET_FEATURE request sets the UF0 device status register L (UF0DSTL) and UF0 EPn status register L (UF0EnSL) (n = 0 to 2) when ACK is received in the status stage. If the E0HALT bit of the UF0E0SL register is set, a STALL response is made in the status stage or data stage of control transfer for a request other than the GET_STATUS Endpoint0 request, SET_FEATURE Endpoint0 request, and a request generated by the CPUDEC interrupt request, until the CLEAR_FEATURE Endpoint0 request is...
Page 277 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (2) Processing The processing of an automatic request in the Default state, Addressed state, and Configured state is described below. Remark Default state: State in which an operation is performed with the Default address Addressed state: State after an address has been allocated Configured state: State after SET_CONFIGURATION wValue = 1 has been correctly received (a) CLEAR_FEATURE() request...
Page 278 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (c) GET_DESCRIPTOR() request If the subject descriptor has a length that is a multiple of wMaxPacketSize, a Null packet is returned to indicate the end of the data stage. If the length of the descriptor at this time is less than the wLength value, the entire descriptor is returned;...
Page 279 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (e) GET_STATUS() request A STALL response is made in the data stage if any of wValue, wIndex, or wLength is other than the values shown in Table 12-3. A STALL response is also made in the data stage if the target is an interface or an endpoint that does not exist.
Page 280 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (g) SET_CONFIGURATION() request If any of wValue, wIndex, or wLength is other than the values shown in Table 12-3, a STALL response is made in the status stage. • Default state: The CONF bit of the UF0 mode status register (UF0MODS) and the UF0 configuration register (UF0CNF) are set to 1 if the specified configuration value is 1 when the SET_CONFIGURATION() request has been received.
Page 281: Other Requests
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (i) SET_INTERFACE() request If wLength is other than the values shown in Table 12-3, if wIndex is other than the value set to the UF0 active interface number register (UF0AIFN), or if wValue is other than the value set to the UF0 active alternative setting register (UF0AAS), a STALL response is made in the status stage.
Page 282: Register Configuration
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) 12.4 Register Configuration 12.4.1 Control registers (1) UF0 EP0NAK register (UF0E0N) This register controls NAK of Endpoint0 (except an automatically executed request). This register can be read or written in 8-bit units (however, bit 0 can only be read). It takes five USB clocks to reflect the status on this register after the UF0FIC0 and UF0FIC1 registers have been set.
Page 283 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Next, the procedure of a SETUP transaction that uses IN/OUT tokens is explained below. (a) When IN token is used (except a request automatically executed by hardware) FW should be used to clear the PROT bit of the UF0IS1 register to 0 after receiving the CPUDEC interrupt and before reading data from the UF0E0ST register.
Page 284 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (2) UF0 EP0NAKALL register (UF0E0NA) This register controls NAK to all the requests of Endpoint0. It is also valid for automatically executed requests. This register can be read or written in 8-bit units. Address After reset UF0E0NA EP0NKA...
Page 285 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (3) UF0 EPNAK register (UF0EN) This register controls NAK of endpoints other than Endpoint0. This register can be read or written in 8-bit units (however, bit 0 can only be read). The BKO2NK bit can be written only when the BKO2NKM bit of the UF0ENM register is 1 and the BKO1NK bit can be written only when the BKO1NKM bit of the UF0ENM register is 1.
Page 286 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position Bit name Function BKI1NK This bit controls NAK to Endpoint1 (bulk 1 transfer (IN)). 1: Do not transmit NAK. 0: Transmit NAK (default value). This bit is cleared to 0 only when the FIFO connected to the SIE side of the UF0BI1 register (64-byte FIFO of bank configuration) cannot receive data.
Page 287 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (4) UF0 EPNAK mask register (UF0ENM) This register controls masking a write access to the UF0EN register. This register can be read or written in 8-bit units. Be sure to clear bits 7 to 3, 1, and 0. If these bits are set to 1, the operation is not guaranteed. Address After reset UF0ENM...
Page 288 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (5) UF0 SNDSIE register (UF0SDS) This register performs manipulation such as no handshake. It can directly manipulate the pins of SIE. This register can be read or written in 8-bit units. Be sure to clear bit 2. If it is set to 1, the operation is not guaranteed. Address After reset UF0SDS...
Page 289 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (6) UF0 CLR request register (UF0CLR) This register indicates the target of the received CLEAR_FEATURE request. This register is read-only, in 8-bit units. This register is meaningful only when an interrupt request is generated. Each bit is set to 1 after completion of the status stage, and automatically cleared to 0 when this register is read.
Page 290 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (7) UF0 SET request register (UF0SET) This register indicates the target of the automatically processed SET_XXXX (except SET_INTERFACE) request. This register is read-only, in 8-bit units. This register is meaningful only when an interrupt request is generated. Each bit is set to 1 after completion of the status stage, and automatically cleared to 0 when this register is read.
Page 291 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (8) UF0 EP status 0 register (UF0EPS0) This register indicates the USB bus status and the presence or absence of register data. This register is read-only, in 8-bit units. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 2) and the current setting of the interface.
Page 292 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (9) UF0 EP status 1 register (UF0EPS1) This register indicates the USB bus status and the presence or absence of register data. This register is read-only, in 8-bit units. Address After reset UF0EPS1 RSUM FF68H Bit position Bit name...
Page 293 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (10) UF0 EP status 2 register (UF0EPS2) This register indicates the USB bus status and the presence or absence of register data. This register is read-only, in 8-bit units. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 2) and the current setting of the interface.
Page 294 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (11) UF0 INT status 0 register (UF0IS0) This register indicates the interrupt source. If the contents of this register are changed, the INTUSB0B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSB0B) is generated from USBF, the FW must read this register to identify the interrupt source.
Page 295 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position Bit name Function EPHALT This bit indicates that an endpoint has stalled. 1: Endpoint has stalled (interrupt request is generated). 0: Endpoint has not stalled (default value). This bit is also set to 1 when an endpoint has stalled by setting FW. Identify the endpoint that has stalled, by referencing the UF0EPS2 register.
Page 296 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (12) UF0 INT status 1 register (UF0IS1) This register indicates the interrupt source. If the contents of this register are changed, the INTUSB0B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSB0B) is generated from USBF, the FW must read this register to identify the interrupt source.
Page 297 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position Bit name Function This bit is set to 1 when the stage of control transfer has changed to the status stage. It is valid for both FW-processed and hardware-processed requests. This bit is also set to 1 when the stage of control transfer (without data) has changed to the status stage.
Page 298 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (13) UF0 INT status 2 register (UF0IS2) This register indicates the interrupt source. If the contents of this register are changed, the INTUSB1B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSB1B) is generated from USBF, the FW must read this register to identify the interrupt source.
Page 299 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (14) UF0 INT status 3 register (UF0IS3) This register indicates the interrupt source. If the contents of this register are changed, the INTUSB1B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSB1B) is generated from USBF, the FW must read this register to identify the interrupt source.
Page 300 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (15) UF0 INT status 4 register (UF0IS4) This register indicates the interrupt source. If the contents of this register are changed, the INTUSB2B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSB2B) is generated from USBF, the FW must read this register to identify the interrupt source.
Page 301 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (16) UF0 INT mask 0 register (UF0IM0) This register controls masking of the interrupt sources indicated by the UF0IS0 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request (INTUSB0B) from USBF by writing 1 to the corresponding bit of this register.
Page 302 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (17) UF0 INT mask 1 register (UF0IM1) This register controls masking of the interrupt sources indicated by the UF0IS1 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request (INTUSB0B) from USBF by writing 1 to the corresponding bit of this register.
Page 303 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (18) UF0 INT mask 2 register (UF0IM2) This register controls masking of the interrupt sources indicated by the UF0IS2 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request (INTUSB1B) from USBF by writing 1 to the corresponding bit of this register.
Page 304 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (19) UF0 INT mask 3 register (UF0IM3) This register controls masking of the interrupt sources indicated by the UF0IS3 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request (INTUSB1B) from USBF by writing 1 to the corresponding bit of this register.
Page 305 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (20) UF0 INT mask 4 register (UF0IM4) This register controls masking of the interrupt sources indicated by the UF0IS4 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request (INTUSB2B) from USBF by writing 1 to the corresponding bit of this register.
Page 306 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (21) UF0 INT clear 0 register (UF0IC0) This register controls clearing the interrupt sources indicated by the UF0IS0 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register.
Page 307 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (22) UF0 INT clear 1 register (UF0IC1) This register controls clearing the interrupt sources indicated by the UF0IS1 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register.
Page 308 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (23) UF0 INT clear 2 register (UF0IC2) This register controls clearing the interrupt sources indicated by the UF0IS2 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register.
Page 309 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (24) UF0 INT clear 3 register (UF0IC3) This register controls clearing the interrupt sources indicated by the UF0IS3 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register.
Page 310 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (25) UF0 INT clear 4 register (UF0IC4) This register controls clearing the interrupt sources indicated by the UF0IS4 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register.
Page 311 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (26) UF0 FIFO clear 0 register (UF0FIC0) This register clears each FIFO. This register is write-only, in 8-bit units. If this register is read, 00H is read. FW can clear the target FIFO by writing 1 to the corresponding bit of this register. The bit to which 1 has been written is automatically cleared to 0.
Page 312 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (27) UF0 FIFO clear 1 register (UF0FIC1) This register clears each FIFO. This register is write-only, in 8-bit units. If this register is read, 00H is read. FW can clear the target FIFO by writing 1 to the corresponding bit of this register. The bit to which 1 has been written is automatically cleared to 0.
Page 313 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (28) UF0 data end register (UF0DEND) This register reports the end of writing to the transmission system. This register is write-only, in 8-bit units (however, bits 7 and 6 can be read and written). If this register is read, 00H is read.
Page 314 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (29) UF0 GPR register (UF0GPR) This register controls USBF and the USB interface. This register is write-only, in 8-bit units. If this register is read, 00H is read. Be sure to clear bits 7 to 2. FW can reset the USBF by writing 1 to bit 0 of this register.
Page 315 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (30) UF0 mode control register (UF0MODC) This register controls CPUDEC processing. This register can be read or written in 8-bit units. By setting each bit of this register, the setting of the UF0MODS register can be changed. The bit of this register is automatically cleared to 0 only at hardware reset and when the MRST bit of the UF0GRP register has been set to 1.
Page 316 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (31) UF0 mode status register (UF0MODS) This register indicates the configuration status. This register is read-only, in 8-bit units. Address After reset UF0MODS CDCGD MPACK DFLT CONF FF2FH Bit position Bit name Function CDCGD This bit specifies whether CPUDEC processing is performed for the GET_DESCRIPTOR Configuration request.
Page 317 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (32) UF0 active interface number register (UF0AIFN) This register sets the valid Interface number that correctly responds to the GET/SET_INTERFACE request. Because Interface 0 is always valid, Interfaces 1 to 4 can be selected. This register can be read or written in 8-bit units.
Page 318 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (33) UF0 active alternative setting register (UF0AAS) This register specifies a link between the Interface number and Alternative Setting. This register can be read or written in 8-bit units. µ USBF of the PD78F0730 can set a five-series Alternative Setting (Alternate Setting 0, 1, 2, 3, and 4 can be defined) and a two-series Alternative Setting (Alternative Setting 0 and 1 can be defined) for one Interface.
Page 319 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (34) UF0 alternative setting status register (UF0ASS) This register indicates the current status of the Alternative Setting. This register is read-only, in 8-bit units. Check this register when the SET_INT interrupt request has been issued. The value received by the SET_INTERFACE request is reflected on the UF0IFn register (n = 0 to 4) as well as on this register.
Page 320 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (35) UF0 endpoint 1 interface mapping register (UF0E1IM) This register specifies for which Interface and Alternative Setting Endpoint1 is valid. This register can be read or written in 8-bit units. The setting of this register and the Alternative Setting selected by the SET_INTERFACE request indicate whether Endpoint1 currently...
Page 321 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (36) UF0 endpoint 2 interface mapping register (UF0E2IM) This register specifies for which Interface and Alternative Setting Endpoint2 is valid. This register can be read or written in 8-bit units. The setting of this register and the Alternative Setting selected by the SET_INTERFACE request indicate whether Endpoint2 currently...
Page 322: Data Hold Registers
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) 12.4.2 Data hold registers (1) UF0 EP0 read register (UF0E0R) The UF0E0R register is a 64-byte FIFO that stores the OUT data sent from the host in the data stage of control transfer to/from Endpoint0. This register is read-only, in 8-bit units.
Page 323 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-2. Operation of UF0E0R Register FIFO Normal hard- Normal completion Abnormal ware completion of reception reception clear of reception Status of UF0E0R register EP0NKR bit of Hardware clear UF0E0N register EP0R bit of Hardware clear UF0EPS0 register...
Page 324 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (3) UF0 EP0 setup register (UF0E0ST) The UF0E0ST register holds the SETUP data sent from the host. This register is read-only, in 8-bit units. A write access to this register is ignored. The UF0E0ST register always writes data when a SETUP transaction has been received. The hardware sets the PROT bit of the UF0IS1 register when it has correctly received the SETUP transaction.
Page 325 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-3. Operation of UF0E0ST Register (a) Normal Completion of Completion of normal reception of normal reception of SETUP token SETUP token Status of UF0E0ST register FW processing Hardware processing CPUDEC bit of Hardware clear UF0IS1 register INT clear INT clear...
Page 326 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (4) UF0 EP0 write register (UF0E0W) The UF0E0W register is a 64-byte FIFO that stores the IN data (passes it to SIE) sent to the host in the data stage to Endpoint0. This register is write-only, in 8-bit units. When this register is read, 00H is read. The hardware transmits data to the USB bus in synchronization with an IN token only when the EP0NKW bit of the UF0E0N register is set to 1 (when NAK is not transmitted).
Page 327 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-4. Operation of UF0E0W Register (a) 16-byte transmission Trans- Trans- trans- mission mission mission completed completed starts Trans- Trans- cannot be mission mission reception received reception starts starts Status of UF0E0W register 16-byte transfer 16-byte transfer Re-transfer Hardware...
Page 328 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (5) UF0 bulk out 1 register (UF0BO1) The UF0BO1 register is a 64-byte × 2 FIFO that stores data for Endpoint2. This register consists of two banks of 64-byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU sides.
Page 329 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-5. Operation of UF0BO1 Register (1/2) (a) Operation example 1 Reception Reception Status of FIFO toggle FIFO toggle completed completed UF0BO1 register Reception transmission starts transmission SIE side FIFO_0 FIFO_1 FIFO_0 FIFO_1 FIFO_0 FIFO_1 CPU side Reading...
Page 330 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-5. Operation of UF0BO1 Register (2/2) (b) Operation example 2 Status of Reception Reception Reception Reception FIFO FIFO UF0BO1 register starts completed starts completed toggle toggle Null Null reception reception completed completed transmission transmission SIE side FIFO_0...
Page 331 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (6) UF0 bulk out 1 length register (UF0BO1L) The UF0BO1L register stores the length of the data held by the UF0BO1 register. This register is read-only, in 8-bit units. A write access to this register is ignored. The UF0BO1L register always updates the received data length while it is receiving data.
Page 332 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (7) UF0 bulk in 1 register (UF0BI1) The UF0BI1 register is a 64-byte × 2 FIFO that stores data for Endpoint1. This register consists of two banks of 64-byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU sides.
Page 333 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-6. Operation of UF0BI1 Register (1/3) (a) Operation example 1 Transmission Transmission FIFO toggle FIFO toggle completed completed Transmission Status of reception starts reception UF0BI1 register side FIFO_0 FIFO_1 FIFO_0 FIFO_1 FIFO_0 FIFO_1 side Writing Writing...
Page 334 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-6. Operation of UF0BI1 Register (2/3) (b) Operation example 2 ACK cannot reception reception be received FIFO toggle Transmission Transmission Transmission transmission Status of completed starts completed starts UF0BI1 register side FIFO_0 FIFO_1 FIFO_1 FIFO_0 side...
Page 335 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-6. Operation of UF0BI1 Register (3/3) (c) Operation example 3 Transmission Transmission completed completed FIFO toggle FIFO toggle Transmission Status of reception starts reception UF0BI1 register side FIFO_0 FIFO_1 FIFO_0 FIFO_1 FIFO_0 FIFO_1 side FIFO Writing...
Page 336: Request Data Registers
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) 12.4.3 Request data registers (1) UF0 device status register L (UF0DSTL) This register stores the value that is to be returned in response to the GET_STATUS Device request. This register can be read or written in 8-bit units. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Device request.
Page 337 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (2) UF0 EP0 status register L (UF0E0SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint0 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1.
Page 338 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (3) UF0 EP1 status register L (UF0E1SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint1 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1.
Page 339 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (4) UF0 EP2 status register L (UF0E2SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint2 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1.
Page 340 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (5) UF0 address register (UF0ADRS) This register stores the device address. This register is read-only, in 8-bit units. The device address sent by the SET_ADDRESS request is analyzed and the resultant value is automatically written to this register.
Page 341 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (6) UF0 configuration register (UF0CNF) This register stores the value that is to be returned in response to the GET_CONFIGURATION request. This register is read-only, in 8-bit units. When the SET_CONFIGURATION request is received, its wValue is automatically written to this register. When a change of the value of this register from 00H to other than 00H is detected, the CONF bits of UF0MODS register are set to 1.
Page 342 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (7) UF0 interface 0 register (UF0IF0) This register stores the value that is to be returned in response to the GET_INTERFACE wIndex = 0 request. This register is read-only, in 8-bit units. When the SET_INTERFACE request is received, its wValue is automatically written to this register. If the SET_INTERFACE request is processed by FW, wIndex and wValue are decoded, and the setting of endpoint is automatically changed.
Page 343 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (8) UF0 interface 1 to 4 registers (UF0IF1 to UF0IF4) These registers store the value that is to be returned in response to the GET_INTERFACE wIndex = n request (n = 1 to 4). These registers are read-only, in 8-bit units.
Page 344 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (9) UF0 descriptor length register (UF0DSCL) This register stores the length of the value that is to be returned in response to the GET_DESCRIPTOR Configuration request. The value of this register is the number of bytes of all the descriptors set by the UF0CIEn register minus 1 (n = 0 to 255).
Page 345 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (10) UF0 device descriptor registers 0 to 17 (UF0DD0 to UF0DD17) These registers store the value to be returned in response to the GET_DESCRIPTOR Device request. These registers can be read or written in 8-bit units. However, data can be written to these registers only when the EP0NKA bit is set to 1.
Page 346 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (11) UF0 configuration/interface/endpoint descriptor registers 0 to 255 (UF0CIE0 to UF0CIE255) These registers store the value to be returned in response to the GET_DESCRIPTOR Configuration request. These registers can be read or written in 8-bit units. However, data can be written to these registers only when the EP0NKA bit is set to 1.
Page 347 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Table 12-7. Data of UF0CIEn Register (a) Configuration descriptor (9 bytes) Offset Field Name Contents bLength Size of this descriptor bDescriptorType Descriptor type wTotalLength Lower value of the total number of bytes of Configuration, all Interface, and all Endpoint descriptors Higher value of the total number of bytes of Configuration, all Interface, and all Endpoint descriptors...
Page 348: Peripheral Control Register
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) 12.4.4 Peripheral control register (1) USB function 0 buffer control register (UF0BC) This register performs enable control and floating control on the input buffer of the USB function. This register can be read or written in 8-bit units. Address After reset UF0BC...
Page 349 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) The following flowcharts illustrate the program execution when the host is disconnected and then reconnected, and the program execution when power is supplied. Figure 12-7. Flowchart of Program When Host Is Disconnected and Then Reconnected START Checks status of pin interrupt detecting host...
Page 350 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-8. Flowchart of Program When Power Is Supplied START Masks INTUSBnB and INTRSUM interrupts Starts USBF clock supply Initializes register area, enables measures against floating Checks status of pin interrupt detecting host connection status Host connected? Unmasks USB-related interrupts and discards...
Page 351: Stall Handshake Or No Handshake
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) 12.5 STALL Handshake or No Handshake Errors of USBF are defined to be handled as follows. Transfer Type Transaction Target Error Type Function Processing Packet Response Control transfer/ IN/OUT/SETUP Token Endpoint not supported No response None bulk transfer Endpoint transfer...
Page 352: Register Values In Specific Status
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) 12.6 Register Values in Specific Status Table 12-8. Register Values in Specific Status (1/2) Register Name After CPU Reset (RESET) After Bus Reset UF0E0N register Value is held. UF0E0NA register Value is held. UF0EN register Value is held.
Page 353 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Table 12-8. Register Values in Specific Status (2/2) Register Name After CPU Reset (RESET) After Bus Reset Note 1 UF0E0R register Undefined Value is held. UF0E0L register Value is held. UF0E0ST register Note 1 UF0E0W register Undefined Value is held.
Page 354 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) 12.7 FW Processing The following FW processing is performed. • Setting processing on device side for the SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE, and CLEAR_FEATURE requests during enumeration processing • Analysis and processing of XXXXStandard, XXXXClass, and XXXXVendor requests not subject to automatic processing •...
Page 355: Fw Processing
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Table 12-9. FW-Supported Standard Requests Request Reception Processing/ Explanation Side Frequency CLEAR_FEATURE Interface Automatic It is considered that this request does not come to Interface STALL response because there is no function selector value, though it is reserved for bmRequestType.
Page 356: Initialization Processing
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) 12.7.1 Initialization processing Initialization processing is executed in the following two ways. • Initialization of request data register • Setting of interrupt When the request data register is initialized, data for the GET_XXXX request to which a value is to be automatically returned is written and an endpoint is allocated to an interface.
Page 357 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-10. Initialization of Request Data Register Area The value of 0XH depends on the power supply method. • SFPW = 1: Self-powered UF0DSTL register = 0XH • SFPW = 0: Bus-powered n = 0 to 2. Setting is unnecessary if the target UF0EnSL register = 00H endpoint is not used.
Page 358 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-12. Setting of Interrupt START Mask the interrupt source to avoid issuance of an unnecessary Setting of UF0IMn register interrupt request (INTUSBmB). Remark n = 0 to 4 m = 0 where n = 0, 1 m = 1 where n = 2, 3 m = 2 where n = 4 Preliminary User’s Manual U19014EJ1V0UD...
Page 359: Interrupt Servicing
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) 12.7.2 Interrupt servicing The following flowchart illustrates how an interrupt is serviced. Figure 12-13. Interrupt Servicing START INTUSBaB active (a = 0 to 2) INTUSB2B = 0? Masking ID bit INTUSB0B = 0? (n = 0, 1) (m = 2, 3) Reading UF0IS4 register Reading UF0ISn register...
Page 360: Usb Main Processing
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) 12.7.3 USB main processing USB main processing involves processing USB transactions. The types of transactions to be processed are as follows. • Fully automatically processed request for control transfer • Automatically processed requests for control transfer (SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE, CLEAR_FEATURE) •...
Page 361 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-14. Automatically Processed Requests for Control Transfer START Receiving SETUP token Decoding request CLEAR_FEATURE? CLEAR_FEATURE processing See Figure 12-15 CLEAR_FEATURE Processing. SET_FEATURE? SET_FEATURE processing : See Figure 12-16 SET_FEATURE Processing. SET_CONFIGURATION? SET_CONFIGURATION processing : See Figure 12-17 SET_CONFIGURATION Processing.
Page 362 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-15. CLEAR_FEATURE Processing Set the corresponding bit for the value of 0XH. UF0CLR register = 0XH The EPHALT bit of the UF0IS0 register is cleared to 0 only when all Halt Features are cleared. CLRRQ = 1 (UF0IS0) Clearing UF0DSTL register...
Page 363 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-16. SET_FEATURE Processing Set the corresponding bit for the value of 0XH. UF0SET register = 0XH The EPHALT bit of the UF0IS0 register is not set to 1 by setting the UF0DSTL register. SETRQ = 1 (UF0IS0) Setting UF0DSTL...
Page 364 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-17. SET_CONFIGURATION Processing SETCON = 1 (UF0SET) SETRQ = 1 (UF0IS0) CONF = 1 (UF0MODS) Setting UF0CNF register ♦: Processing by hardware Remark Figure 12-18. SET_INTERFACE Processing SETINT = 1 (UF0IS4) Setting UF0ASS register Setting UF0IFn register Remarks 1.
Page 365 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (3) CPUDEC request for control transfer The CPUDEC request can be classified into three types of processing: control transfer (write), control transfer (read), and control transfer (without data). Control transfer (write) indicates a request that uses the OUT transaction in the data stage (e.g., SET_DESCRIPTOR), and control transfer (read) indicates a request that uses the IN transaction in the data stage (e.g., GET_DESCRIPTOR).
Page 366 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-19. CPUDEC Request for Control Transfer (2/12) (a) Token phase (2/2) It is judged whether the request decoded by the Supported request? device is supported. Reading UF0ISn register Request that uses control transfer (IN), such as Control transfer (read)? GET_DESCRIPTOR String PROT = 1?
Page 367 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-19. CPUDEC Request for Control Transfer (3/12) (b) Control transfer (read) (1/4) IN token received? Transmitting NAK E0IN = 1 (UF0IS1) INTUSB0B active Reading UF0ISn register E0IN = 1? (UF0IS1) Illegal processing E0INM = 1 (UF0IM1) If return data greater than the FIFO size exists, it is divided into FIFO size units and sequentially...
Page 368 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-19. CPUDEC Request for Control Transfer (4/12) (b) Control transfer (read) (2/4) FIFO full? E0DED = 1 (UF0DEND) EP0NKW = 1 (UF0E0N) PROT = 1? (UF0IS1) EP0WC = 1 (UF0FIC0) IN token received? Transmitting data of UF0E0W register ACK received?
Page 369 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-19. CPUDEC Request for Control Transfer (5/12) (b) Control transfer (read) (3/4) E0INDT = 1 (UF0IS1) EP0NKW = 0 (UF0E0N) INTUSB0B active Reading UF0ISn register E0INDT = 1? (UF0IS1) Illegal processing No transmit data? E0INDTC = 0 (UF0IC1) Data of Null packet received?
Page 370 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-19. CPUDEC Request for Control Transfer (6/12) (b) Control transfer (read) (4/4) INTUSB0B active Reading UF0ISn register STG = 1? (UF0IS1) Illegal processing STGM = 1 (UF0IM1) Transmitting ACK SUCES = 1 (UF0IS1) INTUSB0B active Reading UF0ISn register...
Page 371 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-19. CPUDEC Request for Control Transfer (7/12) (c) Control transfer (write) (1/4) OUT token received? Writing UF0E0R register Normal reception? Clearing UF0E0R register E0ODT = 1 (UF0IS1) EP0R = 1 (UF0EPS0) EP0NKR = 1 (UF0E0N) INTUSB0B active Reading UF0ISn register...
Page 372 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-19. CPUDEC Request for Control Transfer (8/12) (c) Control transfer (write) (2/4) E0ODT = 1? (UF0IS1) Illegal processing Updating data length of UF0E0L register Reading UF0E0R register UF0E0L register data is read up to the value read Data length other than 0? by the UF0E0R register.
Page 373 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-19. CPUDEC Request for Control Transfer (9/12) (c) Control transfer (write) (3/4) STG = 1 (UF0IS1) E0IN = 1 (UF0IS1) INTUSB0B active Reading UF0ISn register PROT = 1? (UF0IS1) Clearing read data STG = 1? (UF0IS1) Illegal processing Request processing...
Page 374 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-19. CPUDEC Request for Control Transfer (10/12) (c) Control transfer (write) (4/4) STGM = 1 (UF0IM1) E0INM = 1 (UF0IM1) IN token received? Transmitting data of Null packet ACK received? SUCES = 1 (UF0IS1) E0INDT = 1 (UF0IS1) INTUSB0B active...
Page 375 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-19. CPUDEC Request for Control Transfer (11/12) (d) Control transfer (without data stage) (1/2) IN token of status phase IN token received? E0IN = 1 (UF0IS1) STG = 1 (UF0IS1) INTUSB0B active Reading UF0ISn register PROT = 1? (UF0IS1) Request processing aborted...
Page 376 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-19. CPUDEC Request for Control Transfer (12/12) (d) Control transfer (without data stage) (2/2) E0INM = 1 (UF0IM1) STGM = 1 (UF0IM1) IN token received? Transmitting data of Null packet ACK received? SUCES = 1 (UF0IS1) E0INDT = 1 (UF0IS1) INTUSB0B active...
Page 377 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (4) Processing for bulk transfer (IN) Bulk transfer (IN) is allocated to Endpoint1. The flowchart is shown below. Preliminary User’s Manual U19014EJ1V0UD Downloaded from Elcodis.com electronic components distributor...
Page 378 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-20. Processing for Bulk Transfer (IN) START IN token received? BKI1IN = 1 (UF0IS2) Returning NAK INTUSB1B active Reading UF0IS2 register BKI1IN = 1? (UF0IS2) Illegal processing BKI1INM = 1 (UF0IM2) If return data greater than the FIFO size exists, Writing UF0BI1 register it is divided into FIFO size units and sequentially written, starting from the lowest data byte.
Page 379 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-21. Parallel Processing by Hardware IN token received? Transmitting data of UF0BI1 register ACK received? BKI1NK = 0 (UF0EN) No transmit data? ♦: Processing by hardware Remark Preliminary User’s Manual U19014EJ1V0UD Downloaded from Elcodis.com electronic components distributor...
Page 380 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) (5) Processing for bulk transfer (OUT) Bulk transfer (OUT) is allocated to Endpoint2. The flowchart is shown below. Preliminary User’s Manual U19014EJ1V0UD Downloaded from Elcodis.com electronic components distributor...
Page 381 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-22. Normal Processing for Bulk Transfer (OUT) START OUT token received? Writing UF0BO1 register Normal reception? Clearing UF0BO1 register BKO1DT = 1 (UF0IS3) BKOUT1 = 1 (UF0EPS0) INTUSB1B active Reading UF0IS3 register BKO1DT = 1? (UF0IS3) Illegal processing Updating data length...
Page 382 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) During bulk transfer (OUT), more data may be transmitted from the host than expected by the system. µ Endpoint2 for bulk transfer (OUT) of the PD78F0730 consist of two 64-byte buffers so that NAK responses are suppressed as much as possible and data can be read from the CPU side even while the bus side is being accessed as the transfer rate of the USB bus increases.
Page 383 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-23. Processing If More Data Than Expected by System Is Transmitted (1/2) START OUT token received? Writing UF0BO1 register Normal reception? Clearing UF0BO1 register BKO1DT = 1 (UF0IS3) BKOUT1 = 1 (UF0EPS0) INTUSB1B active OUT token received? Writing UF0BO1 register...
Page 384 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-23. Processing If More Data Than Expected by System Is Transmitted (2/2) Reading UF0BO1 register UF0BO1 register data is read up to the value read by the Data length other than 0? UF0BO1L register. Data length = Data length –...
Page 385: Suspend/Resume Processing
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) 12.7.4 Suspend/Resume processing How Suspend/Resume processing is performed differs depending on the configuration of the system. example is given below. Figure 12-24. Example of Suspend/Resume Processing (1/3) (a) Example of Suspend processing START Suspend detected? RSUSPD = 1 (UF0IS0) RSUM = 1 (UF0EPS1) INTUSB0B...
Page 386 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-24. Example of Suspend/Resume Processing (2/3) (b) Example of Resume processing START Resume detected? RSUSPD = 1 (UF0IS0) RSUM = 0 (UF0EPS1) INTUSB0B active Reading UF0ISn register RSUSPD = 1? (UF0IS0) Illegal processing Reading UF0EPS1 register RSUM = 0? (UF0EPS1)
Page 387 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-24. Example of Suspend/Resume Processing (3/3) (c) Example of Resume processing (when supply of USB clock to USBF is stopped) START Resume detected? INTRSUM active Executing interrupt servicing Supplying USB clock Resume processing ♦: Processing by hardware Remark Preliminary User’s Manual U19014EJ1V0UD...
Page 388: Processing After Power Application
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) 12.7.5 Processing after power application The processing to be performed after power application differs depending on the configuration of the system. One example is given below. Figure 12-25. Example of Processing After Power Application/Power Failure (1/3) (a) Processing after power application (1/2) START START...
Page 389 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-25. Example of Processing After Power Application/Power Failure (2/3) (a) Processing after power application (2/2) Receiving GET_DESCRIPTOR Device request MPACK = 1 (UF0MODS) Receiving SET_ADDRESS request Writing to UF0ADRS register Receiving SET_CONFIGURATION 1 request SETCON = 1 (UF0SET) SETRQ = 1 (UF0IS0)
Page 390 CHAPTER 12 USB FUNCTION CONTROLLER (USBF) Figure 12-25. Example of Processing After Power Application/Power Failure (3/3) (b) Processing on power failure START Power failure Note INTPx active Interrupt servicing Processing such as clearing FIFO or MRST = 1 (UF0GPR) µ Note INTPx means an external interrupt pin of the PD78F0730 (INTP0 to INTP3).
Page 391: Usb Connection Example
CHAPTER 12 USB FUNCTION CONTROLLER (USBF) 12.7.6 USB connection example Figure 12-26. USB Connection Example µ PD78F0730 USBPUC CONNECT UF0GPR 1.5 kΩ ±5 % USBP 27 Ω ±5 % USBM 27 Ω ±5 % (1) Pull-up control of D+ To prohibit connection notification (D+ pull-up) to the USB host/HUB (such as while higher priority processing or initialization processing is under execution), the system must control pull-up of D+ via the USBPUC pin.
Page 392: Chapter 13 Interrupt Functions
CHAPTER 13 INTERRUPT FUNCTIONS 13.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L, PR1H). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated.
Page 393 CHAPTER 13 INTERRUPT FUNCTIONS Table 13-1. Interrupt Source List Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Note 3 Maskable INTLVI Low-voltage detection Internal 0004H INTP0 Pin input edge detection External 0006H INTP1...
Page 394 CHAPTER 13 INTERRUPT FUNCTIONS Figure 13-1. Basic Configuration of Interrupt Function (A) Internal maskable interrupt Internal bus Vector table Priority controller Interrupt address generator request Standby release signal (B) External maskable interrupt (INTP0 to INTP3) Internal bus External interrupt edge enable register (EGP, EGN) Vector table...
Page 395: Registers Controlling Interrupt Functions
CHAPTER 13 INTERRUPT FUNCTIONS 13.3 Registers Controlling Interrupt Functions The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L, IF1H) • Interrupt mask flag register (MK0L, MK0H, MK1L, MK1H) •...
Page 396 CHAPTER 13 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation.
Page 397 CHAPTER 13 INTERRUPT FUNCTIONS Cautions 3. Use the 1-bit memory manipulation instruction (CLR1) for manipulating the flag of the interrupt request flag register. A 1-bit manipulation instruction such as “IF0L.0 = 0;” and “_asm(“clr1 IF0L, 0”);” should be used when describing in C language, because assembly instructions after compilation must be 1-bit memory manipulation instructions (CLR1).
Page 398 CHAPTER 13 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set by a 16-bit memory manipulation instruction.
Page 399 CHAPTER 13 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory manipulation instruction.
Page 400 CHAPTER 13 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP3. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to 00H.
Page 401 CHAPTER 13 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW.
Page 402: Interrupt Servicing Operations
CHAPTER 13 INTERRUPT FUNCTIONS 13.4 Interrupt Servicing Operations 13.4.1 Maskable interrupt acknowledgement A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
Page 403 CHAPTER 13 INTERRUPT FUNCTIONS Figure 13-7. Interrupt Request Acknowledgement Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated with ××PR = 0?
Page 404: Software Interrupt Request Acknowledgement
CHAPTER 13 INTERRUPT FUNCTIONS Figure 13-8. Interrupt Request Acknowledgement Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock) Figure 13-9.
Page 405: Multiple Interrupt Servicing
CHAPTER 13 INTERRUPT FUNCTIONS 13.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgement enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgement becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgement.
Page 406 CHAPTER 13 INTERRUPT FUNCTIONS Figure 13-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI...
Page 407 CHAPTER 13 INTERRUPT FUNCTIONS Figure 13-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx RETI (PR = 0) IE = 1 IE = 0...
Page 408: Interrupt Request Hold
CHAPTER 13 INTERRUPT FUNCTIONS 13.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgement is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 409: Chapter 14 Standby Function
CHAPTER 14 STANDBY FUNCTION 14.1 Standby Function and Configuration 14.1.1 Standby function The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high-speed system clock oscillator, internal high-speed oscillator, or internal low-speed oscillator is operating before the HALT mode is set, oscillation of each clock continues.
Page 410 CHAPTER 14 STANDBY FUNCTION (1) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked.
Page 411 CHAPTER 14 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released.
Page 412: Standby Function Operation
CHAPTER 14 STANDBY FUNCTION 14.2 Standby Function Operation 14.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, or internal high-speed oscillation clock. The operating statuses in the HALT mode are shown below.
Page 413 CHAPTER 14 STANDBY FUNCTION Table 14-1. Operating Statuses in HALT Mode HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on Internal High-Speed X1 Clock (f External Main System Clock...
Page 414 CHAPTER 14 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed.
Page 415 CHAPTER 14 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 14-4.
Page 416: Stop Mode
CHAPTER 14 STANDBY FUNCTION Table 14-2. Operation in Response to Interrupt Request in HALT Mode Release Source MK×× PR×× Operation × Maskable interrupt Next address request instruction execution × Interrupt servicing execution Next address instruction execution × Interrupt servicing execution ×...
Page 417 CHAPTER 14 STANDBY FUNCTION Table 14-3. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on Internal High-Speed X1 Clock (f External Main System Clock...
Page 418 CHAPTER 14 STANDBY FUNCTION Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware. 2.
Page 419 CHAPTER 14 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 14-6.
Page 420 CHAPTER 14 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 14-7.
Page 421: Chapter 15 Reset Function
CHAPTER 15 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.
Page 422 Figure 15-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF LVIRF Watchdog timer reset signal Clear Clear Reset signal to LVIM/LVIS register RESET Power-on-clear circuit reset signal Reset signal Low-voltage detector reset signal Caution An LVI circuit internal reset does not reset the LVI circuit. Remarks 1.
Page 423 CHAPTER 15 RESET FUNCTION Figure 15-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Reset processing Normal operation Reset period CPU clock Normal operation...
Page 424 CHAPTER 15 RESET FUNCTION Figure 15-4. Timing of Reset in STOP Mode by RESET Input Wait for oscillation STOP instruction execution accuracy stabilization Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Reset processing Normal...
Page 425 CHAPTER 15 RESET FUNCTION Table 15-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock Operation stopped Operation stopped (pin is I/O port mode) Clock input invalid (pin is I/O port mode) EXCLK Operation stopped Flash memory...
Page 426 CHAPTER 15 RESET FUNCTION Table 15-2. Hardware Statuses After Reset Acknowledgment (1/3) Hardware After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined...
Page 427 CHAPTER 15 RESET FUNCTION Table 15-2. Hardware Statuses After Reset Acknowledgment (2/3) Hardware Status After Reset Note 1 Acknowledgment 8-bit timer H1 Compare registers 01, 11 (CMP01, CMP11) Mode register (TMHMD1) Carrier control register 1 (TMCYC1) Note 2 Watchdog timer Enable register (WDTE) 1AH/9AH Serial interface UART6...
Page 428 CHAPTER 15 RESET FUNCTION Table 15-2. Hardware Statuses After Reset Acknowledgment (3/3) Hardware Status After Reset Note 1 Acknowledgment USB function controller UF0 EP0 write register (UF0E0W) USBF UF0 bulk-out 1 register (UF0BO1) Undefined UF0 bulk-out 1 length register (UF0BO1L) UF0 bulk-in 1 register (UF0BI1) UF0 device status register (UF0DSTL) UF0 EPn status register L (UF0EPnSL) (n = 0 to 2)
Page 429: Register For Confirming Reset Source
CHAPTER 15 RESET FUNCTION 15.1 Register for Confirming Reset Source µ Many internal reset generation sources exist in the PD78F0730. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset by power-on-clear (POC) circuit, and reading RESF set RESF to 00H.
Page 430: Chapter 16 Power-On-Clear Circuit
CHAPTER 16 POWER-ON-CLEAR CIRCUIT 16.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. • Generates internal reset signal at power on. Note In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) , the reset signal is released when the supply ) exceeds 2.7 V ±0.2 V.
Page 431: Configuration Of Power-On-Clear Circuit
CHAPTER 16 POWER-ON-CLEAR CIRCUIT 16.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 16-1. Figure 16-1. Block Diagram of Power-on-Clear Circuit Internal reset signal − Reference voltage source 16.3 Operation of Power-on-Clear Circuit In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) •...
Page 432 CHAPTER 16 POWER-ON-CLEAR CIRCUIT Figure 16-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Set LVI to be Set LVI to be Set LVI to be used for reset used for interrupt used for reset...
Page 433: Cautions For Power-On-Clear Circuit
CHAPTER 16 POWER-ON-CLEAR CIRCUIT 16.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage (V ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 434 CHAPTER 16 POWER-ON-CLEAR CIRCUIT Figure 16-3. Example of Software Processing After Reset Release (2/2) • Checking reset source Check reset source WDTRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF register = 1? Reset processing by low-voltage detector Power-on-clear/external reset generated...
Page 435: Chapter 17 Low-Voltage Detector
CHAPTER 17 LOW-VOLTAGE DETECTOR 17.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has the following functions. • Compares supply voltage (V ) and detection voltage (V ), and generates an internal interrupt signal or internal reset signal when V <...
Page 436: Registers Controlling Low-Voltage Detector
CHAPTER 17 LOW-VOLTAGE DETECTOR 17.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. • Low-voltage detection register (LVIM) • Low-voltage detection level selection register (LVIS) • Port mode register 12 (PM12) Preliminary User’s Manual U19014EJ1V0UD Downloaded from Elcodis.com electronic components distributor...
Page 437 CHAPTER 17 LOW-VOLTAGE DETECTOR (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets LVIM to 00H. Figure 17-2. Format of Low-Voltage Detection Register (LVIM) Note 1 Address: FFBEH After reset: 00H...
Page 438 CHAPTER 17 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation input sets LVIS to 00H. Figure 17-3. Format of Low-Voltage Detection Level Selection Register (LVIS) Address: FFBFH After reset: 00H Symbol...
Page 439: Operation Of Low-Voltage Detector
CHAPTER 17 LOW-VOLTAGE DETECTOR 17.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. (1) Used as reset Compare the supply voltage (V ) and detection voltage (V ), generate an internal reset signal when V <...
Page 440: When Used As Reset
CHAPTER 17 LOW-VOLTAGE DETECTOR 17.4.1 When used as reset (1) When detecting level of supply voltage (V • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bit 0 (LVIS0) of the low-voltage detection level selection register (LVIS). <3>...
Page 441 CHAPTER 17 LOW-VOLTAGE DETECTOR Figure 17-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (V In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Supply voltage (V 2.7 V (TYP.) = 1.59 V (TYP.) Time LVIMK flag Note 1...
Page 442: When Used As Interrupt
CHAPTER 17 LOW-VOLTAGE DETECTOR 17.4.2 When used as interrupt (1) When detecting level of supply voltage (V • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bit 0 (LVIS0) of the low-voltage detection level selection register (LVIS). <3>...
Page 443 CHAPTER 17 LOW-VOLTAGE DETECTOR Figure 17-6. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (V In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Supply voltage (V 2.7 V(TYP.) = 1.59 V (TYP.) Time LVIMK flag (set by software) <1>...
Page 444: Cautions For Low-Voltage Detector
CHAPTER 17 LOW-VOLTAGE DETECTOR 17.5 Cautions for Low-Voltage Detector In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage ), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status.
Page 445 CHAPTER 17 LOW-VOLTAGE DETECTOR Figure 17-7. Example of Software Processing After Reset Release (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset Note Check the reset source Initialization Initialize the port. processing <1>...
Page 446 CHAPTER 17 LOW-VOLTAGE DETECTOR Figure 17-7. Example of Software Processing After Reset Release (2/2) • Checking reset source Check reset source WDTRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF register = 1? Power-on-clear/external reset generated Reset processing by low-voltage detector Preliminary User’s Manual U19014EJ1V0UD...
Page 447: Chapter 18 Option Byte
CHAPTER 18 OPTION BYTE 18.1 Functions of Option Bytes µ The flash memory at 0080H to 0084H of the PD78F0730 is an option byte area. When power is turned on or when the device is restarted from the reset status, the device automatically references the option bytes and sets specified functions.
Page 448: Format Of Option Byte
CHAPTER 18 OPTION BYTE 18.2 Format of Option Byte The format of the option byte is shown below. Figure 18-1. Format of Option Byte (1/2) Note Address: 0080H/1080H WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 LSROSC WINDOW1 WINDOW0 Watchdog timer window open period Setting prohibited 100% WDTON...
Page 449 CHAPTER 18 OPTION BYTE Figure 18-1. Format of Option Byte (2/2) Notes 1, 2 Address: 0081H/1081H POCMODE POCMODE POC mode selection 1.59 V POC mode (default) 2.7 V/1.59 V POC mode Notes 1. POCMODE can only be written by using a dedicated flash programmer. It cannot be set during self- programming or boot swap operation during self-programming (at this time, 1.59 V POC mode (default) is set).
Page 450 CHAPTER 18 OPTION BYTE Here is an example of description of the software for setting the option bytes. CSEG AT 0080H OPTION: DB ; Enables watchdog timer operation (illegal access detection operation), ; Window open period of watchdog timer: 100%, ;...
Page 451: Chapter 19 Flash Memory
CHAPTER 19 FLASH MEMORY µ PD78F0730 incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. 19.1 Internal Memory Size Switching Register The internal memory capacity can be selected using the internal memory size switching register (IMS). IMS is set by an 8-bit memory manipulation instruction.
Page 452: Internal Expansion Ram Size Switching Register
CHAPTER 19 FLASH MEMORY 19.2 Internal Expansion RAM Size Switching Register The internal expansion RAM capacity can be selected using the internal expansion RAM size switching register (IXS). IXS is set by an 8-bit memory manipulation instruction. Reset signal generation sets IXS to 0CH. Caution Be sure to set to 08H after a reset release.
Page 453: Writing With Flash Memory Programmer
CHAPTER 19 FLASH MEMORY 19.3 Writing with Flash Memory Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer. (1) On-board programming µ The contents of the flash memory can be rewritten after the PD78F0730 has been mounted on the target system.
Page 454 CHAPTER 19 FLASH MEMORY Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 19-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode (4.5 to 5.5 V) VDD2 /RESET FLMD0 WRITER INTERFACE...
Page 455 CHAPTER 19 FLASH MEMORY Figure 19-4. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode (4.5 to 5.5 V) Note VDD2 Note /RESET FLMD0 WRITER INTERFACE Note The above figure illustrates an example of wiring when using the clock output from the PG-FP4 or FL-PR4. When using the clock output from the PG-FPL3 or FP-LITE3, connect CLK to X1/P121 (pin 8), and connect its inverted signal to X2/EXCLK/P122 (pin 7).
Page 456: Programming Environment
CHAPTER 19 FLASH MEMORY 19.4 Programming Environment µ The environment required for writing a program to the flash memory of the PD78F0730 is illustrated below. Figure 19-5. Environment for Writing Program to Flash Memory FLMD0 RS-232C Axxxx Bxxxxx Cxxxxxx STATVE PG-FP4 RESET µ...
Page 457 CHAPTER 19 FLASH MEMORY (2) UART6 Transfer rate: 115200 bps Figure 19-7. Communication with Dedicated Flash Memory Programmer (UART6) FLMD0 FLMD0 Axxxx Bxxxxx /RESET RESET Cxxxxxx STATVE PG-FP4 SI/RxD TxD6 µ Dedicated flash SO/TxD RxD6 PD78F0730 memory programmer Note Note EXCLK Note The above figure illustrates an example of wiring when using the clock output from the PG-FP4 or FL-PR4.
Page 458: Connection Of Pins On Board
CHAPTER 19 FLASH MEMORY 19.6 Connection of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.
Page 459 CHAPTER 19 FLASH MEMORY (1) Signal collision If the dedicated flash memory programmer (output) is connected to a pin (input) of a serial interface connected to another device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state.
Page 460: Reset Pin
CHAPTER 19 FLASH MEMORY 19.6.3 RESET pin If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator.
Page 461: Power Supply
CHAPTER 19 FLASH MEMORY 19.6.7 Power supply To use the supply voltage output of the flash memory programmer, connect the V pin to V of the flash memory programmer, and the V pin to GND of the flash memory programmer. However, be sure to connect the V and V pins to V...
Page 462: Flash Memory Programming Mode
CHAPTER 19 FLASH MEMORY 19.7.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the µ PD78F0730 in the flash memory programming mode. To set the mode, set the FLMD0 pin to V and clear the reset signal.
Page 463: Selecting Communication Mode
CHAPTER 19 FLASH MEMORY 19.7.3 Selecting communication mode µ In the PD78F0730, a communication mode is selected by inputting pulses (up to 11 pulses) to the FLMD0 pin after the dedicated flash memory programming mode is entered. These FLMD0 pulses are generated by the flash memory programmer.
Page 464: Communication Commands
CHAPTER 19 FLASH MEMORY 19.7.4 Communication commands µ PD78F0730 communicates with the dedicated flash memory programmer by using commands. The signals µ sent from the flash memory programmer to the PD78F0730 are called commands, and the signals sent from the µ...
Page 465: Security Settings
CHAPTER 19 FLASH MEMORY 19.8 Security Settings µ PD78F0730 supports a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the Security Set command. The security setting is valid when the programming mode is set next.
Page 466 CHAPTER 19 FLASH MEMORY Table 19-8. Relationship Between Enabling Security Function and Command (1) During on-board/off-board programming Valid Security Executed Command Batch Erase (Chip Erase) Block Erase Write Note Prohibition of batch erase (chip erase) Cannot be erased in batch Blocks cannot be Can be performed erased.
Page 467: Flash Memory Programming By Self-Programming
CHAPTER 19 FLASH MEMORY 19.9 Flash Memory Programming by Self-Programming µ PD78F0730 supports a self-programming function that can be used to rewrite the flash memory via a user µ program. Because this function allows a user application to rewrite the flash memory by using the PD78F0730 self- programming library, it can be used to upgrade the program in the field.
Page 468 CHAPTER 19 FLASH MEMORY The following figure illustrates a flow of rewriting the flash memory by using a self programming sample library. Figure 19-16. Flow of Self Programming (Rewriting Flash Memory) Start of self programming FLMD0 pin Low level → High level FlashStart Setting operating environment FlashEnv...
Page 469: Boot Swap Function
CHAPTER 19 FLASH MEMORY 19.9.1 Boot swap function If rewriting the boot area has failed during self-programming due to a power failure or some other cause, the data in the boot area may be lost and the program may not be restarted by resetting. The boot swap function is used to avoid this problem.
Page 470 CHAPTER 19 FLASH MEMORY Figure 19-18. Example of Executing Boot Swapping Block number Erasing block 4 Erasing block 5 Erasing block 6 Erasing block 7 Program Program Program Program Boot Program Program Program cluster 1 Program Program Program 1 0 0 0 H Boot program Boot program Boot program...
Page 471: Chapter 20 On-Chip Debug Function
NEC Electronics is not liable for problems occurring when the on-chip debug function is used.
Page 472: On-Chip Debug Security Id
CHAPTER 20 ON-CHIP DEBUG FUNCTION µ Figure 20-2. Connection Example of QB-78K0MINI and PD78F0730 (When OCD1A and OCD1B Are Used) µ PD78F0730 QB-78K0MINI target connector FLMD0 FLMD0 Note Target reset RESET_IN RESET_OUT RESET OCD1A/P31 Note OCD1B/P32 Note Make pull-down resistor 470 Ω or more (10 kΩ: recommended). Connect the FLMD0 pin as follows when performing self programming by means of on-chip debugging.
Page 473: Chapter 21 Instruction Set
CHAPTER 21 INSTRUCTION SET µ This chapter lists each instruction set of the PD78F0730 in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). 21.1 Conventions Used in Operation List 21.1.1 Operand identifiers and specification methods Operands are written in the “Operand”...
Page 474: Description Of Operation Column
CHAPTER 21 INSTRUCTION SET 21.1.2 Description of operation column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 475: Operation List
CHAPTER 21 INSTRUCTION SET 21.2 Operation List Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − r ← byte 8-bit data r, #byte transfer (saddr) ← byte saddr, #byte − sfr ← byte sfr, #byte −...
Page 476 CHAPTER 21 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − rp ← word 16-bit data MOVW rp, #word transfer (saddrp) ← word saddrp, #word − sfrp ← word sfrp, #word AX ←...
Page 477 CHAPTER 21 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A, CY ← A − byte × × × 8-bit A, #byte operation (saddr), CY ← (saddr) − byte × ×...
Page 478 CHAPTER 21 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A ← A ∨ byte × 8-bit A, #byte operation (saddr) ← (saddr) ∨ byte × saddr, #byte − A ← A ∨ r ×...
Page 479 CHAPTER 21 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − AX, CY ← AX + word × × × 16-bit ADDW AX, #word operation − AX, CY ← AX − word ×...
Page 480 CHAPTER 21 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 CY ← CY ∧ (saddr.bit) × AND1 CY, saddr.bit manipulate − CY ← CY ∧ sfr.bit × CY, sfr.bit − CY ← CY ∧ A.bit ×...
Page 481 CHAPTER 21 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) Call/return CALL !addr16 PC ← addr16, SP ← SP − 2 −...
Page 482 CHAPTER 21 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 Conditional saddr.bit, $addr16 branch − PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 −...
Page 483: Instructions Listed By Addressing Type
CHAPTER 21 INSTRUCTION SET 21.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Note Second Operand #byte saddr !addr16 [DE]...
Page 484 CHAPTER 21 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note Second Operand #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW...
Page 485 CHAPTER 21 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP Preliminary User’s Manual U19014EJ1V0UD Downloaded from...
Page 486: Chapter 22 Electrical Specifications (Target)
NEC Electronics is not liable for problems occurring when the on-chip debug function is used.
Page 487 CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET) Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Page 488 CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET) X1 Oscillator Characteristics = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = EV = EV = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit 4.0 V ≤ V ≤...
Page 489 CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET) Internal Oscillator Characteristics = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = EV = 0 V) Resonator Parameter Conditions MIN. TYP. MAX. Unit ≥ 16 MHz internal oscillator Internal high-speed oscillation RSTS = 1 14.4 16.0...
Page 490 CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET) DC Characteristics (1/3) = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = EV = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.0 V ≤ V ≤ 5.5 V −3.0 Note 1 Output current, high...
Page 491 CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET) DC Characteristics (2/3) = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = EV = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high P12, P13, P15, P16 0.7V P00, P01, P10, P11, P14, P17, P30 to P33, P120 to 0.8V...
Page 492 CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET) DC Characteristics (3/3) = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = EV = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit µ Input leakage current, P00, P01, P10 to P17, LIH1 high P30 to P33, P60, P61,...
Page 493 CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET) AC Characteristics (1) Basic operation = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = EV = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit µ 4.0 V ≤ V ≤...
Page 494 CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET) vs. V (Main System Clock Operation) 20.0 10.0 Guaranteed operation range 0.01 Supply voltage V AC Timing Test Points (except Excluding External Main System Clock input) 0.8V 0.8V Test points 0.2V 0.2V External Main System Clock Timing EXCLK EXCLKL EXCLKH...
Page 495 CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET) TI Timing TIL0 TIH0 TI000, TI010 TIL5 TIH5 TI50, TI51 Interrupt Request Input Timing INTL INTH INTP0 to INTP3 RESET Input Timing RESET Preliminary User’s Manual U19014EJ1V0UD Downloaded from Elcodis.com electronic components distributor...
Page 496 CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET) (2) Serial interface = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = EV = EV = 0 V) (a) UART6 (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate kbps...
Page 497 CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET) Serial Transfer Timing CSI10: KCYm SCK10 SIKm KSIm SI10 Input data KSOm SO10 Output data Remark m = 1, 2 Preliminary User’s Manual U19014EJ1V0UD Downloaded from Elcodis.com electronic components distributor...
Page 498 CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET) = −40 to +85°C, V 1.59 V POC Circuit Characteristics (T = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage 1.44 1.59 1.74 : 0 V → change inclination of V Power voltage rise inclination 0.75 V/ms...
Page 499 CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET) = −40 to +85°C, V ≤ V ≤ 5.5 V, V LVI Circuit Characteristics (T = EV = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection Supply voltage level LVIS0 = 0 4.14 4.24 4.34...
Page 500 CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET) = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, 3.0 V ≤ V ≤ 3.6 V, V Note 1 USBF Characteristics (T = EV = EV USBREGC Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 2 USBM, USBP pin output rise/fall...
Page 501 CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET) Flash Memory Programming Characteristics = −40 to +85°C, 4.0 V ≤ V ≤ 5.5 V, V = EV = EV = 0 V) Basic characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit supply current = 17.6 MHz (MAX.) 11.0 Notes 1, 2 Erase time...
Page 502: Chapter 23 Package Drawings
CHAPTER 23 PACKAGE DRAWINGS 30-PIN PLASTIC SSOP (7.62mm (300)) detail of lead end (UNIT:mm) ITEM DIMENSIONS 9.70±0.10 0.30 0.65 (T.P.) NOTE 0.22 +0.10 −0.05 Each lead centerline is located within 0.13 mm of its 0.10±0.05 true position (T.P.) at maximum material condition. 1.30±0.10 1.20 8.10±0.20...
Page 503: Chapter 24 Cautions For Wait
CHAPTER 24 CAUTIONS FOR WAIT 24.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
Page 504: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS µ The following development tools are available for the development of systems that employ the PD78F0730. Figure A-1 shows the development tool configuration. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT compatibles are compatible with PC98-NX series computers.
Page 505 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/2) (1) When using the in-circuit emulator QB-780731 Software package Software package Language processing software Debugging software Assembler package Integrated debugger C compiler package System simulator Device file Note 1 C library source file Control software Project manager Note 2...
Page 506 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/2) (2) When using the on-chip debug emulator QB-78K0MINI Software package Software package Debugging software Language processing software Assembler package Integrated debugger C compiler package System simulator Device file Note 1 C library source file Control software Project manager...
Page 507: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 Development tools (software) common to the 78K/0 Series are combined in this package. 78K/0 Series software package µ Part number: S××××SP78K0 Remark ×××× in the part number differs depending on the host machine and OS used. µ...
Page 508: Control Software
APPENDIX A DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and OS used. µ S××××RA78K0 µ S××××CC78K0 µ S××××CC78K0-L ×××× Host Machine Supply Medium AB17 PC-9800 series, Windows (Japanese version) CD-ROM IBM PC/AT compatibles BB17 Windows (English version) 3P17...
Page 509: Debugging Tools (Hardware)
APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) A.5.1 When using in-circuit emulator QB-780731 Note 1 QB-780731 This in-circuit emulator serves to debug hardware and software when developing application µ In-circuit emulator systems using the PD78F073x. It supports to the integrated debugger (ID78K0-QB). This emulator should be used in combination with a power supply unit and emulation probe, and the USB is used to connect this emulator to the host machine.
Page 510: Debugging Tools (Software)
APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) ID78K0-QB This debugger supports the in-circuit emulators for the 78K/0 Series. The ID78K0-QB is Integrated debugger Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result.
Page 511: Appendix B Register Index
APPENDIX B REGISTER INDEX B.1 Register Index (In Alphabetical Order with Respect to Register Names) 16-bit timer capture/compare register 000 (CR000)....................115 16-bit timer capture/compare register 010 (CR010)....................115 16-bit timer counter 00 (TM00)............................115 16-bit timer mode control register 00 (TMC00) ......................118 16-bit timer output control register 00 (TOC00)......................121 8-bit timer compare register 50 (CR50)........................180 8-bit timer compare register 51 (CR51)........................180...
Page 512 APPENDIX B REGISTER INDEX Interrupt mask flag register 1H (MK1H)........................398 Interrupt mask flag register 1L (MK1L) ........................398 Interrupt request flag register 0H (IF0H) ........................396 Interrupt request flag register 0L (IF0L)........................396 Interrupt request flag register 1H (IF1H) ........................396 Interrupt request flag register 1L (IF1L)........................396 Low-voltage detection level selection register (LVIS)....................438 Low-voltage detection register (LVIM).........................437 Main clock mode register (MCM) ..........................89...
Page 513 APPENDIX B REGISTER INDEX Serial clock selection register 10 (CSIC10).........................258 Serial I/O shift register 10 (SIO10) ..........................256 Serial operation mode register 10 (CSIM10).......................257 Timer clock selection register 50 (TCL50) ........................181 Timer clock selection register 51 (TCL51) ........................181 Transmit buffer register 10 (SOTB10).........................256 Transmit buffer register 6 (TXB6)..........................226 Transmit shift register 6 (TXS6) ..........................226 UF0 active alternative setting register (UF0AAS)......................318...
Page 514 APPENDIX B REGISTER INDEX UF0 INT clear 2 register (UF0IC2) ..........................308 UF0 INT clear 3 register (UF0IC3) ..........................309 UF0 INT clear 4 register (UF0IC4) ..........................310 UF0 INT mask 0 register (UF0IM0) ..........................301 UF0 INT mask 1 register (UF0IM1) ..........................302 UF0 INT mask 2 register (UF0IM2) ..........................303 UF0 INT mask 3 register (UF0IM3) ..........................304 UF0 INT mask 4 register (UF0IM4) ..........................305 UF0 INT status 0 register (UF0IS0)..........................294...
Page 515: Register Index (In Alphabetical Order With Respect To Register Symbol)
APPENDIX B REGISTER INDEX B.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ASIF6: Asynchronous serial interface transmission status register 6................230 ASIM6: Asynchronous serial interface operation mode register 6................227 ASIS6: Asynchronous serial interface reception error status register 6 ..............229 BRGC6: Baud rate generator control register 6 ......................232 CKSR6: Clock selection register 6 ..........................231 CMP01: 8-bit timer H compare register 01........................197...
Page 516 APPENDIX B REGISTER INDEX OSTC: Oscillation stabilization time counter status register ..................90, 410 OSTS: Oscillation stabilization time select register ....................91, 411 P0: Port register 0 .................................77 P1: Port register 1 .................................77 P12: Port register 12 ..............................77 P3: Port register 3 .................................77 P6: Port register 6 .................................77 PCC: Processor clock control register...........................86 PLLC: PLL control register ............................92...
Page 517 APPENDIX B REGISTER INDEX TOC00: 16-bit timer output control register 00 ......................121 TXB6: Transmit buffer register 6 ..........................226 TXS6: Transmit shift register 6............................226 UCKC: USB clock control register..........................93 UF0AAS: UF0 active alternative setting register ......................318 UF0ADRS: UF0 address register..........................340 UF0AIFN: UF0 active interface number register ......................317 UF0ASS: UF0 alternative setting status register......................319 UF0BC: USB function 0 buffer control register......................348 UF0BI1: UF0 bulk in 1 register............................332...
Page 518 APPENDIX B REGISTER INDEX UF0IM1: UF0 INT mask 1 register ..........................302 UF0IM2: UF0 INT mask 2 register ..........................303 UF0IM3: UF0 INT mask 3 register ..........................304 UF0IM4: UF0 INT mask 4 register ..........................305 UF0IS0: UF0 INT status 0 register ..........................294 UF0IS1: UF0 INT status 1 register ..........................296 UF0IS2: UF0 INT status 2 register ..........................298 UF0IS3: UF0 INT status 3 register ..........................299 UF0IS4: UF0 INT status 4 register ..........................300...

NEC mPD78F0730 Preliminary User's Manual

Chapter 1 Outline

Chapter 2 Pin Functions

Chapter 3 Cpu Architecture

Chapter 4 Port Functions

Chapter 5 Clock Generator

Chapter 6 16-Bit Timer/Event Counter 00

Chapter 7 8-Bit Timer/Event Counters 50 and 51

Chapter 8 8-Bit Timer H1

Chapter 9 Watchdog Timer

Chapter 10 Serial Interface Uart6

Chapter 11 Serial Interface Csi10

Chapter 12 Usb Function Controller Usbf

Chapter 13 Interrupt Functions

Chapter 14 Standby Function

Chapter 15 Reset Function

Chapter 16 Power-On-Clear Circuit

Chapter 17 Low-Voltage Detector

Chapter 18 Option Byte

Chapter 19 Flash Memory

Chapter 20 On-Chip Debug Function

Chapter 21 Instruction Set

Chapter 22 Electrical Specifications (Target)

Chapter 23 Package Drawings

Chapter 24 Cautions for Wait

Appendix A Development Tools

Appendix B Register Index

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Summary of Contents for NEC mPD78F0730