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A start condition is output when the IIC control register (IICC0)'s bit 1 (STT) is set (to "1") after a stop condition
has been detected (SPD: Bit 0 = 1 in the IIC status register (IICS0)). When a start condition is detected, IICS0's
bit 1 (STD) is set (to "1").
(2)
Addresses
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected
to the master device via bus lines. Therefore, each slave device connected via the bus lines must have a
unique address.
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address
data matches the data values stored in the slave address register (SVA0). If the address data matches the
SVA0 values, the slave device is selected and communicates with the master device until the master device
transmits a start condition or stop condition.
SCL
SDA
INTIIC0
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.
The slave address and the eighth bit, which specifies the transfer direction as described in "(3) Transfer direction
specification" below, are together written to the IIC shift register (IIC0) and are then output. Received addresses
are written to IIC0.
The slave address is assigned to the high-order 7 bits of IIC0.
234
CHAPTER 10 SERIAL INTERFACE FUNCTION
Figure 10-15. Address
1
2
3
4
5
A6
A5
A4
A3
A2
Address
6
7
8
9
A1
A0
R/W
Note
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