NEC V850/SA1 mPD703015 Preliminary User's Manual page 380

32-/16-bit single-chip microcontrollers
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Instruction Set (alphabetical order) (3/4)
Mnemonic
Operand
SAR
reg1, reg2
rrrrr111111RRRRR
0000000010100000
imm5, reg2
rrrrr010101iiiii
SATADD
reg1, reg2
rrrrr000110RRRRR
imm5, reg2
rrrrr010101iiiii
SATSUB
reg1, reg2
rrrrr000101RRRRR
SATSUBI imm16,
rrrrr110011RRRRR
reg1, reg2
iiiiiiiiiiiiiiii
SATSUBR reg1, reg2
rrrrr000100RRRRR
SETF
cccc, reg2
rrrrr1111110cccc
0000000000000000
SET1
bit#3,
00bbb111110RRRRR
disp16 [reg1]
dddddddddddddddd
SHL
reg1, reg2
rrrrr111111RRRRR
0000000011000000
imm5, reg2
rrrrr010110iiiii
SHR
reg1, reg2
rrrrr1111111cccc
0000000000000000
imm5, reg2
rrrrr010100iiiii
SLD.B
disp7 [ep],
rrrrr0110ddddddd
reg2
SLD.H
disp8 [ep],
rrrrr1000ddddddd
reg2
SLD.W
disp8 [ep],
rrrrr1010ddddddd
reg2
Notes 1.
ddddddd is the higher 7 bits of dip8.
2.
dddddd is the higher 6 bits of disp8.
380
APPENDIX B
LIST OF INSTRUCTION
Op Code
GR [reg2] ← GR [reg2] arithmetically shift
right
GR [reg2] ← GR [reg2] arithmetically shift
right
GR [reg2] ← saturated (GR [reg2] − GR
[reg1])
GR [reg2] ← saturated (GR [reg2] + sign-
extend (imm5))
GR [reg2] ← saturated (GR [reg2] − GR
[reg1])
GR [reg2] ← saturated (GR [reg1] − sign-
extend (imm16))
GR [reg2] ← saturated (GR [reg1] + GR
[reg2])
if conditions are satisfied
then GR [reg2] ← 00000001H
eise GR [reg2] ← 00000000H
adr ← GR [reg1] + sign-extend (disp16)
Z flag ← Not (Load-memory-bit
(adr, bit#3)
Store memory-bit (adr, bit#3, 1)
GR [reg2] ← GR [reg2] logically shift left
by GR [reg1])
GR [reg2] ← GR [reg2] logically shift left
GR [reg2] ← GR [reg2] logically shift right
by GR [reg1]
GR [reg2] ← GR [reg2] logically shift right
adr ← ep + zero-extend (disp7)
GR [reg2] ← sign-extend (Load-memory
(adr, Byte))
adr ← ep + zero-extend (disp7)
Note 1
GR [reg2] ← sign-extend (Load-memory
(adr, Byte))
adr ← ep + zero-extend (disp7)
Note 2
GR [reg2] ← Load-memory (adr, Word)
Execution
Operation
i
1
by GR [reg1]
1
by zero-extend (imm5)
1
1
1
1
1
1
4
1
1
by zero-extend (imm5)
1
1
by zero-extend (imm5)
1
1
1
Flag
Clock
r
l
CY OV
S
Z
×
×
×
1
1
0
×
×
×
1
1
0
×
×
×
×
1
1
×
×
×
×
1
1
×
×
×
×
1
1
×
×
×
×
1
1
×
×
×
×
1
1
1
1
×
4
4
×
×
×
1
1
0
×
×
×
1
1
0
×
×
×
1
1
0
×
×
×
1
1
0
1
2
1
2
1
2
SAT
×
×
×
×
×

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