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Fig. No.
3-1
CPU Address Space...............................................................................................................................
3-2
Image on Address Space .......................................................................................................................
3-3
Memory Map...........................................................................................................................................
3-4
Internal ROM Area (with Mask ROM Internal Version) ...........................................................................
3-5
External Memory Area (when expanded to 64 K, 256 K, or 1 Mbytes)...................................................
3-6
External Memory Area (when expanded to 4 Mbytes)............................................................................
3-7
Memory Expansion Mode Register (MM) Format ...................................................................................
3-8
Memory Address Output Mode Register (MAM) Format ........................................................................
3-9
Recommended Memory Map (Flash Memory Internal Version) .............................................................
4-1
Example of Inserting Wait States............................................................................................................
5-1
Non-Maskable Interrupt Processing .......................................................................................................
5-2
Accepting Non-Maskable Interrupt Request ...........................................................................................
5-3
RETI Instruction Processing ...................................................................................................................
5-4
Rising Edge Specification Register (EGP0) Format ...............................................................................
5-5
Falling Edge Specification Register (EGN0) Format ..............................................................................
5-6
Maskable Interrupt Processing ...............................................................................................................
5-7
RETI Instruction Processing ...................................................................................................................
5-8
Example of Interrupt Nesting Process ....................................................................................................
5-9
Example of Processing Interrupt Requests Simultaneously Generated .................................................
5-10
Interrupt Control Register (xxICn) Format ..............................................................................................
5-11
Inservice Priority Register (ISPR) Format...............................................................................................
5-12
Watchdog Timer Mode Register (WDTM) Format ..................................................................................
5-13
Software Exception Processing ..............................................................................................................
5-14
RETI Instruction Processing ...................................................................................................................
5-15
Exception Trap Processing.....................................................................................................................
5-16
RETI Instruction Processing ...................................................................................................................
5-17
Pipeline Operation at Interrupt Request Acknowledge ...........................................................................
6-1
Format of Processor Clock Control Register (PCC) ...............................................................................
6-2
Format of Power Saving Control Register (PSC)....................................................................................
6-3
Format of Oscillation Stabilization Time Select Register (OSTS)...........................................................
7-1
Block Diagram of TM0 and TM1 .............................................................................................................
7-2
Format of 16-Bit Timer Mode Control Register 0, 1 (TMC0, TMC1) .......................................................
7-3
Format of Capture/Compare Control Register 0, 1 (CRC0, CRC1) ........................................................
7-4
Format of 16-Bit Timer Output Control Register 0, 1 (TOC0, TOC1)......................................................
7-5
Format of Prescaler Mode Register 0 (PRM0)........................................................................................
7-6
Format of Prescaler Mode Register 1 (PRM1)........................................................................................
7-7
Control Register Settings When Timer 0 Operates as Interval Timer.....................................................
7-8
Configuration of Interval Timer ...............................................................................................................
7-9
Timing of Interval Timer Operation .........................................................................................................
7-10
Control Register Settings in PPG Output Operation...............................................................................
LIST OF FIGURES (1/5)
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