Error Tolerance (When K = 0), Including Sampling Errors - NEC V850/SA1 mPD703015 Preliminary User's Manual

32-/16-bit single-chip microcontrollers

Table of Contents

Figure 10-33. Error Tolerance (when k = 0), including Sampling Errors

Basic timing

(clock cycle T)

High-speed clock

(clock cycle T')

enabling normal

Low-speed clock

(clock cycle T")

enabling normal

Remark T: 5-bit counter's source clock cycle

Baud rate error tolerance (when k = 0) =

SERIAL INTERFACE FUNCTION

× 100 = 4.8438 (%)

Sampling error