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(2)
Watchdog timer mode register (WDTM)
This register sets the operating mode of the watchdog timer, and enables and disables counting.
Data can be written to it only in a sequence of specific instructions so that its contents are not eas-
ily rewritten in case of program hang-up. See also WCMD register.
Once the watchdog timer is started (RUN = 1) after reset, this register cannot be changed.
WDTM is set by an 8/1-bit memory manipulation instruction.
Cautions: 1. The WDTM4 bit has to set to "1" at the initialisation of the WDT
2. WDTM register setting by DMA transfer is prohibited. This registers should be
written with STORE instruction execution by CPU only.
7
6
WDTM
RUN
0
RUN
0
1
WDTM4
Note 2
1
1
Notes: 1. If RUN is set to "1" once, the register cannot be cleared to "0" by software. Therefore, when
the count starts, the count cannot be stopped except by RESET input.
2. The WDTM4 bit has to set to "1" at the initialisation of the WDT.
Cautions: 1. Data is set to the CKC register by the following sequence:
•
Write any 8-bit data to the command register (WCMD)
•
Write the set data to the destination register (WDTM)
2. If RUN is set to "1" and the watchdog timer is cleared, the actual overflow time
may be up to 2
360
Chapter 12 Watchdog Timer Function
Figure 12-3: Watchdog Timer Mode Register (WDTM)
5
4
3
0
WDTM4 WDTM3
Operating Mode Selection for the Watchdog Timer
After Reset: disable count (writing during counting: clear old count)
After Reset: start counting (writing during counting: clear old count)
WDTM3
Watchdog Timer Operation Mode Selection
Watchdog timer mode 1
0
(Non-maskable interrupt occurs upon generation of an overflow)
Watchdog timer mode 2
1
(RESET operation is activated upon generation of an overflow)
12
/f
seconds less than the set time.
XX
Preliminary User's Manual U15839EE1V0UM00
2
1
0
0
0
0
FFFF F572H
Address
R/W
After reset
R/W
Note 1
00H
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