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3.4.9 Specific registers
Specific registers are registers that are protected from being written with illegal data due to erroneous program
execution, etc. The write access of these specific registers is executed in a specific sequence, and if abnormal store
operations occur, it is notified by the system status register (SYS). The V850/SA1 has two specific registers, the
power save control register (PSC) and processor clock control register (PCC). For details of the PSC register, refer to
6.3.1 (2), and for details of the PCC register, refer to 6.3.1 (1).
The following sequence shows the data setting of the specific registers.
<1> DMA operation is disabled.
<2> Set the PSW NP bit to 1 (interrupt disabled).
<3> Write any 8-bit data in the command register (PRCMD).
<4> Write the set data in the specific registers (by the following instructions).
• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
<5> Return the PSW NP bit to 0 (interrupt disable canceled).
<6> Insert the NOP instructions (2 or 5 instructions).
<7> Enable DMA operation if required.
No special sequence is required when reading the specific registers.
Caution 1. If an interrupt request is accepted between the time PRCMD is issued <3> and the specific
register write operation <4> that follows immediately after, the write operation to the specific
register is not performed and a protection error (PRERR bit of SYS register is "1") may occur.
Therefore, set the NP bit of PSW to 1 <2> to disable the acceptance of INT/NMI.
The above also applies when a bit manipulation instruction is used to set a specific register.
Moreover, to ensure that the execution routine following release of the STOP/IDLE mode is
performed correctly, insert the NOP instruction as a dummy instruction <6>. If the value of
the ID bit of PSW does not change as the result of execution of the instruction to return the NP
bit to 0 <5>, insert two NOP instructions, and if the value of the ID bit of PSW changes, insert
five NOP instructions.
80
CHAPTER 3
CPU FUNCTIONS
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