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Figure 10-27. Example of Slave to Master Communication
(when 9-clock Wait Is Selected for Both Master and Slave) (1/3)
Processing by master device
IIC0 ← address
IIC0
ACKD
STD
SPD
WTIM
H
ACKE
H
MSTS
STT
L
SPT
WREL
INTIIC0
TRC
Transfer lines
1
SCL
A6
SDA
Start condition
Processing by slave device
IIC0
ACKD
STD
SPD
WTIM
H
H
ACKE
MSTS
L
L
STT
L
SPT
WREL
L
INTIIC0
TRC
Note To cancel slave wait, write "FFH" to IIC0 or set WREL.
CHAPTER 10 SERIAL INTERFACE FUNCTION
(a) Start condition ~ address
2
3
4
5
6
7
A5
A4
A3
A2
A1
A0
IIC0 ← FFH Note
Note
8
9
1
2
R
D7
D6
IIC0 ← data
3
4
5
6
D5
D4
D3
D2
277
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