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15.1 General
When low-level input occurs at the RESET pin, a system reset is performed and the various on-chip hardware
devices are reset to their initial settings. In addition, oscillation of the main clock is stopped during the reset period,
although oscillation of the sub clock continues.
When the input at the RESET pin changes from low level to high level, the reset status is canceled and the CPU
resumes program execution. The contents of the various registers should be initialized within the program as
necessary.
An on-chip noise elimination circuit uses analog delay to prevent noise-related misoperation of the RESET pin.
15.2 Pin Operations
During the system reset period, high impedance is set at almost all pins (all pins except for RESET, X2, XT2, V
V
, AV
, AV
, BV
, BV
SS
DD
SS
DD
Accordingly, if connected to an external memory device, be sure to attach pull-up (or pull-down) resistance for
each pin in ports 3 to 6 and ports 9 to 11. If such resistance is not attached, high impedance will be set for these
pins, which could damage the memory devices. Likewise, make sure the pins are handled so as to prevent such
effects at the signal outputs and output ports used by on-chip peripheral I/O functions.
X1
RESET
Internal system
reset signal
CHAPTER 15
, and V
).
SS
PP
Figure 15-1. System Reset Timing
Analog delay
Analog
delay
Eliminated as noise
Reset is accepted
RESET FUNCTION
Hi-Z
Oscillation stabilization time
Analog delay
30.84 ms (during 17-MHz operation)
Reset is canceled
,
DD
357
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