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(when 9-clock Wait Is Selected for Both Master and Slave) (3/3)
Processing by master device
IIC0 ← data
IIC0
ACKD
STD
SPD
WTIM
H
ACKE
H
MSTS
STT
SPT
WREL
L
INTIIC0
TRC
Transmit
H
Transfer lines
SCL
D7
SDA
Processing by slave device
IIC0
ACKD
STD
SPD
WTIM
H
H
ACKE
MSTS
L
STT
L
SPT
L
WREL
INTIIC0
TRC
L
Receive
Note To cancel slave wait, write "FFH" to IIC0 or set WREL.
276
CHAPTER 10 SERIAL INTERFACE FUNCTION
Figure 10-26. Example of Master to Slave Communication
(c) Stop condition
1
2
3
4
5
6
D6
D5
D4
D3
D2
IIC0 ← FFH Note
Note
7
8
9
D1
D0
Stop
condition
IIC0 ← FFH Note
Note
IIC0 ← address
(When SPIE = 1)
1
2
A6
A5
Start
condition
(When SPIE = 1)
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