NEC V850/SA1 mPD703015 Preliminary User's Manual page 224

32-/16-bit single-chip microcontrollers
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WREL
0
Does not cancel wait
1
Cancels wait. This setting is automatically cleared after wait is canceled.
Condition for clearing (WREL = 0)
• Automatically cleared after execution
• When RESET is input
SPIE
0
Disable
1
Enable
Condition for clearing (SPIE = 0)
• Cleared by instruction
• When RESET is input
WTIM
0
Interrupt request is generated at the eighth clock's falling edge.
Master mode : After output of eight clocks, clock output is set to low level and wait is set.
Slave mode : After input of eight clocks, the clock is set to low level and wait is set for master device.
1
Interrupt request is generated at the ninth clock's falling edge.
Master mode : After output of nine clocks, clock output is set to low level and wait is set.
Slave mode : After input of nine clocks, the clock is set to low level and wait is set for master device.
This bit's setting is invalid during an address transfer and is valid as the transfer is completed. When in master mode,
a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a
local address, a wait is inserted at the falling edge of the ninth clock after an ACK signal is issued. When the slave
device has received an extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM = 0)
• Cleared by instruction
• When RESET is input
Note This flag's signal is invalid when IICE = 0.
224
CHAPTER 10 SERIAL INTERFACE FUNCTION
Figure 10-9. Format of IIC Control Register (IICC0) (2/4)
Note
Enable/disable Generation of Interrupt Request when Stop Condition is Detected
Note
Control of Wait and Interrupt Request Generation
Note
Cancel Wait
Condition for setting (WREL = 1)
• Set by instruction
Condition for setting (SPIE = 1)
• Set by instruction
Condition for setting (WTIM = 1)
• Set by instruction

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