Table of Contents
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{ External bus interface
{ On-chip memory
{ Interrupts and exceptions
{ I/O lines
{ Timer/counter
{ Watch timer
{ Watchdog timer
{ Serial interface (SIO)
{ A/D converter
{ DMA controller
{ RTP
{ Clock generator
{ Power-saving functions
{ Package
{ CMOS structure
22
CHAPTER 1
INTRODUCTION
16-bit data bus (address/data multiplex)
Address bus: separate output enabled
Bus hold function
External wait function
µ PD703015, 703015Y (ROM: 128 Kbytes, RAM: 4 Kbytes)
µ PD70F3017, 70F3017Y (Flash memory: 256 Kbytes, RAM: 8 Kbytes)
External interrupts: 8 (including NMIs)
Internal interrupts: 30 sources
Exceptions: 1 source
Interrupt priority levels are freely selectable (among 8 levels)
Total: 85 (13 input ports and 72 I/O ports)
16-bit timer: 2 channels (PWM output)
8-bit timer: 4 channels (PWM output, cascade connection enabled)
When operating under subsystem or main system clock: 1 channel
1 channel
Asynchronous serial interface (UART)
Clock-synchronized serial interface (CSI)
C) ( µ PD703015Y or 70F3017Y only)
2
2
I
C bus interface (I
UART: 1 ch
CSI: 1 ch
UART/CSI: 1 ch
2
I
C/CSI: 1 ch
UART dedicated baud rate generator: 2 channels
10-bit resolution: 12 channels
On-chip RAM ←→ on-chip peripheral I/O: 3 channels
8 bits × 1 ch or 4 bits × 2 ch
During main system clock or subsystem clock operation
5-level CPU clock (including slew rate and sub operations)
HALT/IDLE/STOP modes
100-pin plastic LQFP (fine pitch, 14 × 14 mm, resin thickness: 1.40 mm)
121-pin fine pitch BGA (12 × 12 mm)
All static circuits
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