NEC V850/SA1 mPD703015 Preliminary User's Manual page 115

32-/16-bit single-chip microcontrollers
Table of Contents

Advertisement

CHAPTER 5
Main routine
EI
Interrupt request i
(level 2)
Interrupt request k
Interrupt request l
Interrupt request n
(level 2)
Interrupt request o
Interrupt
(level 3)
request p
(level 2)
Interrupt request s
Interrupt request u
(level 1)
Notes 1. Lower default priority
2. Higher default priority
INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 5-8. Example of Interrupt Nesting Process (2/2)
Processing of i
EI
Interrupt
request j
(level 3)
(level 1)
Processing of j
Processing of l
Interrupt
request m
(level 3)
(level 1)
Processing of n
Processing of m
Processing of o
Processing of p
EI
EI
Interrupt
request q
Interrupt
(level 1)
request r
(level 0)
Processing of s
Interrupt
request t
Note 1
(level 2)
Note 2
(level 2)
Processing of u
Processing of t
Processing of k
Interrupt request j is kept pending because its
priority is lower than that of i. k that occurs after j
is accepted because it has the higher priority.
Interrupt requests m and n are kept pending
because processing of l is performed in the
interrupt disabled status.
Pending interrupt requests are accepted after
processing of interrupt request l.
At this time, interrupt requests n is accepted first
even though m has occurred first because the
priority of n is higher than that of m.
Processing of q
Processing of r
EI
EI
If levels 3 to 0 are accepted
Pending interrupt requests t and u are accepted
after processing of s.
Because the priorities of t and u are the same, u is
accepted first because it has the higher default
priority, regardless of the order in which the
interrupt requests have been generated.
115

Advertisement

Table of Contents
loading

Table of Contents