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(2) Capture/compare control register 0, 1 (CRC0, CRC1)
This register controls the operation of the capture/compare register n (CRn0 and CRn1).
CRCn is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CRC0 and CRC1 to 00H.
Figure 7-3. Format of Capture/Compare Control Register 0, 1 (CRC0, CRC1)
At reset: 00H
7
CRCn
0
(n = 0, 1)
CRCn2
0
1
CRCn1
0
1
CRCn0
0
1
Cautions 1. Before setting CRCn, be sure to stop the timer operation.
2. When the mode in which the timer is cleared and started on coincidence between TMn
and CRn0 is selected by the 16-bit timer mode control register n (TMCn), do not specify
CRn0 as a capture register.
3. Capture cannot be performed when both the rising edge and falling edge are selected as
the valid edge of TIn0.
CHAPTER 7
TIMER/COUNTER FUNCTION
R/W
Address: FFFFF20AH, FFFFF21AH
6
5
0
0
Selects Operation Mode of CRn1
Operates as compare register.
Operates as capture register.
Selects Capture Trigger of CRn0
Captured at valid edge of TIn1.
Captured in reverse phase of valid edge of TIn0.
Selects Operation Mode of CRn0
Operates as compare register.
Operates as capture register.
4
3
2
0
0
CRCn2
1
0
CRCn1
CRCn0
153
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