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(3) On-chip peripheral I/O area
A 4-Kbyte area of addresses FFF000H to FFFFFFH is reserved as an on-chip peripheral I/O area. The V850/SA1
is provided with a 1-Kbyte area of addresses FFF000H to FFF3FFH as a physical on-chip peripheral I/O area,
and its image can be seen on the rest of the area (FFF400H to FFFFFFH).
Peripheral I/O registers associated with the operation mode specification and the state monitoring for the on-chip
peripherals are all memory-mapped to the on chip peripheral I/O area. Program fetches are not allowed in this
area.
xxFFFFFFH
xxFFFC00H
xxFFFBFFH
xxFFF800H
xxFFF7FFH
xxFFF400H
xxFFF3FFH
xxFFF000H
Cautions 1. The least significant bit of an address is not decoded since all registers reside on an even
address. If an odd address (2n + 1) in the peripheral I/O area is referenced, the register at
the next lowest even address (2n) will be accessed.
2. If a register that can be accessed in byte units is accessed in half-word units, the higher 8
bits become undefined, if the access is a read operation. If a write access is made, only
the data in the lower 8 bits is written to the register.
3. If a register with n address that can be accessed only in halfword units is accessed with a
word operation, the operation is replaced with two halfword operations.
operation (lower 16 bits) accesses to the register with n address and the second
operation (higher 16 bits) accesses to the register with n + 2 address.
4. If a register with n address that can be accessed in word units is accessed with a word
operation, the operation is replaced with two halfword operations. The first operation
(lower 16 bits) accesses to the register with n address and the second operation (higher
16 bits) accesses to the register with n + 2 address.
5. Addresses that are not defined as registers are reserved for future expansion. If these
addresses are accessed, the operation is undefined and not guaranteed.
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CHAPTER 3
CPU FUNCTIONS
Image
Image
Image
Image
Physical peripheral I/O
3FFH
Peripheral I/O
000H
The first
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