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(3) Pulse width measurement with free running counter and two capture registers
When the 16-bit timer register n (TMn) is used as a free running counter (refer to Figure 7-17), the pulse width of
the signal input to the TIn0 pin can be measured.
When the edge specified by bits 4 and 5 (ESn00 and ESn01) of the prescaler mode register n (PRMn) is input to
the TIn0 pin, the value of TMn is loaded to the 16-bit capture/compare register n1 (CRn1), and an external
interrupt request signal (INTTMn1) is set.
The value of TMn is also loaded to the 16-bit capture/compare register n0 (CRn0) when an edge reverse to the
one that triggers capturing to CRn1 is input.
The edge of the TIn0 pin is specified by bits 4 and 5 (ESn00 and ESn01) of the prescaler mode register n
(PRMn). The rising or falling edge can be specified.
The valid edge of TIn0 is detected through sampling at a count clock cycle selected by the prescaler mode
register n (PRMn), and the capture operation is not performed until the valid level is detected two times.
Therefore, noise with a short pulse width can be rejected.
Caution If the valid edge of the TIn0 pin is specified to be both the rising and falling edges, the
capture/compare register n0 (CRn0) cannot perform its capture operation.
Figure 7-17. Control Register Settings for Pulse Width Measurement
TMCn
0
0
CRCn
0
0
Remark 0/1: When these bits are reset to 0 or set to 1, the other functions can be used along with the pulse
width measurement function. For details, refer to Figures 7-2 and 7-3.
CHAPTER 7
TIMER/COUNTER FUNCTION
with Free Running Counter and Two Capture Registers
(a) 16-bit timer mode control register 0, 1 (TMC0, TMC1)
TMCn3
0
0
(b) Capture/compare control register 0, 1 (CRC0, CRC1)
0
0
TMCn2
TMCn1
0
1
0/1
CRCn2
CRCn1
0
1
1
OVFn
0
Free running mode
CRCn0
1
CRn0 as capture
register
Captures to CRn0 at
edge reverse to valid
edge of TIn0 pin.
CRn1 as capture
register
165
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