C5.2 Encoding For Tag And Data In The L1 Instruction Cache - ARM Cortex-A35 Technical Reference Manual

C5.2 Encoding for tag and data in the L1 instruction cache
The following table shows the format of the Instruction Cache Tag Read Operation Register and the
Instruction Cache Data Read Operation Register.
The set-index range parameter (S) is determined by the following formula:
S = log (size of the instruction cache in bytes / 2)
2
The following table shows the format of the information in Data Register 0 following an Instruction
Cache Tag Read Operation.
Bits Description
[31] Unused.
[30:29] Valid and set mode:
0b00 A32.
0b01 T32.
0b10 A64.
0b11 Invalid.
[28] Non-secure state (NS).
[27:0] Tag address.
The Instruction Cache Data Read Operation returns two entries from the cache in Data Register 0 and
Data Register 1 corresponding to the 16-bit aligned offset in the cache line:
Data Register 0
Data Register 1
In A32 or A64 state these two fields combined always represent a single predecoded instruction. In T32
state, they can represent any combination of 16-bit and partial or full 32-bit instructions.
100236_0100_00_en
Table C5-3 Instruction cache tag and data location encoding
Bits[19:0] data from cache offset+
Bits[19:0] data from cache offset+
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C5 Direct access to internal memory

C5.2 Encoding for tag and data in the L1 instruction cache

Table C5-4 Instruction cache tag data format
.
0b00
.
0b10
Bit field Description
[31] Cache Way
[30:S] Unused
[S-1:6] Set index
[5:2] Line offset
[1:0] Unused
C5-609