Figure 2-3 Swd Timing Diagrams - ARM DS-5 Manual

Read cycle
DSTREAM Probe output
to SWDIO
DSTREAM Probe output
to SWDCLK
Target output to SWDIO
Write cycle
DSTREAM Probe output
to SWDIO
DSTREAM Probe output
to SWDCLK
Target output to SWDIO
The probe writes data to SWDIO on the falling edge of SWDCLK. The probe reads data from SWDIO
on the rising edge of SWDCLK. The target writes data to SWDIO on the rising edge of SWDCLK. The
target reads data from SWDIO on the rising edge of SWDCLK.
The following table shows the timing requirements for the Serial Wire Debug (SWD):
Related concepts
2.1.1 JTAG port timing characteristics on page 2-23.
2.1.3 About trace signals on page 2-26.
Related references
2.1.2 Serial Wire Debug on page 2-25.
SWD connections on page 2-25.
2.1.3 About trace signals
Data transfer is synchronized by the TRACECLK signal.
Clock frequency
For capturing trace port signals synchronous to TRACECLK, the DSTREAM trace feature supports up
to 600Mbps per trace signal using DDR clocking mode, or up to 480Mbps using SDR clocking mode.
The following figure and table describe the timing for TRACECLK:
ARM 100956_0527_00_en
Stop Park
T high T lo w
T os
Tri-State
Stop Park
T is
Tri-State
Parameter Min Max Description
T 10ns 500μs SWDCLK HIGH period
high
T
10ns 500μs SWDCLK LOW period
low
T
-5ns 5ns SWDIO Output skew to falling edge SWDCLK
os
T
4ns - Input Setup time required between SWDIO and rising edge SWDCLK
is
T
1ns - Input Hold time required between SWDIO and rising edge SWDCLK
ih
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2 ARM DSTREAM Target Interface Connections
Tri-State
Acknowledge
Tri-State
T ih
Acknowledge Data
2.1 Signal descriptions
Data Data
Tri-State
Data Parity

Figure 2-3 SWD timing diagrams

Table 2-2 SWD timing requirements
Parity Start
Start
Tri-State
2-26