Reference Clock Distribution And Selection; Functional Description; Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Reference Clock Distribution and Selection

Functional Description

For proper high-speed operation, the GTH transceiver requires a high-quality, low-jitter
reference clock. Because of the shared PMA PLL architecture inside the GTH Quad, each
reference clock sources all four lanes. The reference clock is used to produce the PLL clock,
which is divided by one or four to make individual TX and RX serial clocks and parallel
clocks for each GTH transceiver.
The GTH Quad reference clock is provided through the REFCLK port. There are two ways
to drive the REFCLK port:
•
•
Using the dedicated clock routing provides the best possible clock to the GTH Quad. Each
GTH Quad has a dedicated clock pin, represented by the IBUFDS_GTHE1 primitive, that
can be used to drive the dedicated clock routing.
This clocking section shows how to select the dedicated clocks for use by one or more GTH
Quads.

Ports and Attributes

Table 2-4
.
Table 2-4: Reference Clock Selection Ports
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Using an external oscillator to drive GTH dedicated clock routing
Using a clock from a neighboring GTH Quad through GTH dedicated clock routing
(not recommended for GTH transceivers operating a line rates 2.8 Gb/s and above)
defines the reference clock selection ports.
Port
PLLREFCLKSEL[2:0]
REFCLK
TSTREFCLKFAB
TSTREFCLKOUT
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Reference Clock Distribution and Selection
Dir Clock Domain
In DCLK Reserved. Tie these inputs to 000.
In N/A This input is the external jitter stable
clock driven by the IBUFDS_GTHE1
primitive as the reference clock to the
GTHE1_QUAD primitive.
Out N/A This port provides direct access to
the reference clock provided to the
shared PLL in the GTHE1_QUAD
primitive. The clock is routed
through interconnect and can be
used to clock FPGA logic.
Out N/A This port provides direct access to
the reference clock provided to the
shared PLL in the GTHE1_QUAD
primitive. The clock is routed
through the global clock tree (must
be connected through a BUFG) and
can be used to clock FPGA logic. This
port can also connect directly to an
MMCM or BUFR.
Description
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