Rte - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
Hide thumbs Also See for SH7750:
Table of Contents

Advertisement

10.79

RTE

Return from Exception Handling
Format
RTE
Description
This instruction returns from an exception or interrupt handling routine by restoring the PC and
SR values from SPC and SSR. Program execution continues from the address specified by the
restored PC value.
RTE is a privileged instruction, and can only be used in privileged mode. Use of this instruction in
user mode will cause an illegal instruction exception.
Notes
As this is a delayed branch instruction, the instruction following the RTE instruction is executed
before the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction. An exception
must not be generated by the instruction in this instruction's delay slot. If the following instruction
is a branch instruction, it is identified as a slot illegal instruction.
If this instruction is located in the delay slot immediately following a delayed branch instruction, it
is identified as a slot illegal instruction.
The SR value accessed by the instruction in the RTE delay slot is the value restored from SSR by
the RTE instruction. The SR and MD values defined prior to RTE execution are used to fetch the
instruction in the RTE delay slot.
ReTurn from Exception
Summary of Operation
SSR → SR, SPC→ PC
System Control Instruction
(Privileged Instruction)
Delayed Branch Instruction
Instruction Code
0000000000101011 5
Rev. 2.0, 03/99, page 349 of 396
Execution
States
T Bit

Advertisement

Table of Contents
loading

Table of Contents