Hitachi SH7750 Programming Manual page 146

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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Table 7.1
Addressing Modes and Effective Addresses (cont)
Addressing
Instruction
Mode
Format
Register
@(disp:4, Rn) Effective address is register Rn contents with
indirect with
displacement
Indexed
@(R0, Rn)
register
indirect
GBR indirect
@(disp:8,
with
GBR)
displacement
Indexed
@(R0, GBR)
GBR indirect
Rev. 2.0, 03/99, page 132 of 396
Effective Address Calculation Method
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2 (word),
or 4 (longword), according to the operand size.
Rn
disp
(zero-extended)
×
1/2/4
Effective address is sum of register Rn and R0
contents.
Rn
R0
Effective address is register GBR contents with
8-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2 (word),
or 4 (longword), according to the operand size.
GBR
disp
(zero-extended)
×
1/2/4
Effective address is sum of register GBR and R0
contents.
GBR
R0
Rn + disp × 1/2/4
+
+
Rn + R0
GBR
+
+ disp × 1/2/4
+
GBR + R0
Calculation
Formula
Byte: Rn +
disp → EA
Word: Rn +
disp × 2 → EA
Longword:
Rn + disp × 4
→ EA
Rn + R0 → EA
Byte: GBR +
disp → EA
Word: GBR +
disp × 2 → EA
Longword:
GBR + disp ×
4 → EA
GBR + R0 →
EA

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