Fdiv - Hitachi SH7750 Programming Manual

10.30

FDIV

Floating-Point
Division
PR Format
0 FDIV FRm,FRn
1 FDIV DRm,DRn
Description
When FPSCR.PR = 0: Arithmetically divides the single-precision floating-point number in FRn by
the single-precision floating-point number in FRm, and stores the result in FRn.
When FPSCR.PR = 1: Arithmetically divides the double-precision floating-point number in DRn
by the double-precision floating-point number in DRm, and stores the result in DRn.
When FPSCR.enable.O/U/I is set, an FPU exception trap is generated regardless of whether or not
an exception has occurred. When an exception occurs, correct exception information is reflected in
FPSCR.cause and FPSCR.flag, and FRn or DRn is not updated. Appropriate processing should
therefore be performed by software.
Operation
void FDIV(int m,n)
{
pc += 2;
clear_cause();
if((data_type_of(m) == sNaN) ||
(data_type_of(n) == sNaN)) invalid(n);
else if((data_type_of(m) == qNaN) ||
(data_type_of(n) == qNaN)) qnan(n);
else switch (data_type_of(m)){
case NORM: switch (data_type_of(n)){
case PINF:
case NINF:
case PZERO:
case NZERO:
case DENORM:set_E();
default:
}
Rev. 2.0, 03/99, page 254 of 396
Floating-point DIVide
Summary of Operation
FRn/FRm → FRn
DRn/DRm → DRn
/* FDIV FRm,FRn */
inf(n,sign_of(m)^sign_of(n));break;
zero(n,sign_of(m)^sign_of(n));break;
normal_fdiv(m,n);
break;
Floating-Point Instruction
Instruction Code
1111nnnnmmmm0011 10
1111nnn0mmm00011 23
break;
break;
Execution
States T Bit
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