Hitachi SH7750 Programming Manual page 152

Table 7.4 Arithmetic Operation Instructions
Instruction
ADD Rm,Rn
ADD #imm,Rn
ADDC Rm,Rn
ADDV Rm,Rn
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PZ Rn
CMP/PL Rn
CMP/STR Rm,Rn
DIV1 Rm,Rn
DIV0S Rm,Rn
DIV0U
DMULS.L Rm,Rn
DMULU.L Rm,Rn
DT Rn
EXTS.B Rm,Rn
Rev. 2.0, 03/99, page 138 of 396
Operation
Rn + Rm → Rn
Rn + imm → Rn
Rn + Rm + T → Rn, carry → T
Rn + Rm → Rn, overflow → T
When R0 = imm, 1 → T
Otherwise, 0 → T
When Rn = Rm, 1 → T
Otherwise, 0 → T
When Rn ≥ Rm (unsigned),
1 → T
Otherwise, 0 → T
When Rn ≥ Rm (signed), 1 → T
Otherwise, 0 → T
When Rn > Rm (unsigned),
1 → T
Otherwise, 0 → T
When Rn > Rm (signed), 1 → T
Otherwise, 0 → T
When Rn ≥ 0, 1 → T
Otherwise, 0 → T
When Rn > 0, 1 → T
Otherwise, 0 → T
When any bytes are equal,
1 → T
Otherwise, 0 → T
1-step division (Rn ÷ Rm)
MSB of Rn → Q,
MSB of Rm → M, M^Q → T
0 → M/Q/T
Signed, Rn × Rm → MAC,
32 × 32 → 64 bits
Unsigned, Rn × Rm → MAC,
32 × 32 → 64 bits
Rn – 1 → Rn; when Rn = 0,
1 → T
When Rn ≠ 0, 0 → T
Rm sign-extended from
byte → Rn
Instruction Code
0011nnnnmmmm1100 —
0111nnnniiiiiiii —
0011nnnnmmmm1110 —
0011nnnnmmmm1111 —
10001000iiiiiiii —
0011nnnnmmmm0000 —
0011nnnnmmmm0010 —
0011nnnnmmmm0011 —
0011nnnnmmmm0110 —
0011nnnnmmmm0111 —
0100nnnn00010001 —
0100nnnn00010101 —
0010nnnnmmmm1100 —
0011nnnnmmmm0100 —
0010nnnnmmmm0111 —
0000000000011001 —
0011nnnnmmmm1101 —
0011nnnnmmmm0101 —
0100nnnn00010000 —
0110nnnnmmmm1110 —
Privileged T Bit
—
—
Carry
Overflow
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Calculation
result
Calculation
result
0
—
—
Comparison
result
—