10.103 Xtrct - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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10.103 XTRCT

Middle Extraction
from Linked Registers
Format
Summary of Operation
Middle 32 bits of Rm:Rn → Rn
XTRCT Rm,Rn
Description
This instruction extracts the middle 32 bits from the 64-bit contents of linked general registers Rm
and Rn, and stores the result in Rn.
MSB
Operation
XTRCT(long m, long n)
{
unsigned long temp;
temp=(R[m]<<16)&0xFFFF0000;
R[n]=(R[n]>>16)&0x0000FFFF;
R[n]|=temp;
PC+=2;
}
Example
XTRCT R0,R1
Rev. 2.0, 03/99, page 390 of 396
eXTRaCT
LSB
Rm
/* XTRCT Rm,Rn */
;Before execution R0 = H'01234567, R1 = H'89ABCDEF
;After execution
Data Transfer Instruction
Instruction Code
0010nnnnmmmm1101 1
MSB
Rn
R1 = H'456789AB
Execution
States
T Bit
LSB
Rn

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